JPH0223634A - Semiconductor integrated circuit and broadcasting radio receiver using same - Google Patents

Abstract

PURPOSE:To prevent unnecessary radiation and other interference and then, obtain integration of FM front end circuits in the same chips by mounting a shield electrode. CONSTITUTION:As FM front end circuits 1 ate composed of 250 elements, three pieces of mats 16 are prepared; besides, the whole of the FM front end circuits 1 is partitioned every 80-100 elements. Respective circuit elements are housed in K, L and M mats according to the foregoing partitions and connection wiring is arranged. A shield electrode 17 is mounted so that it may cover the upper parts of the K, L and M mats and grounding potential GND is impressed by respective grounding electrode pads 13a and 13b which are installed exclusively in the FM front end circuits 1. Other each circuit block is also housed in respective integral number of the mats 16 in the same way as the above-mentioned means.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor integrated circuit in which circuit blocks such as an FM/AM tuner having different signal frequencies and signal levels are formed on the same semiconductor substrate.

(b) Conventional technology Electronic devices such as TV tuners and FM/AM tuners are
Since the audio signal is extracted from the F (Radio Frequency) signal, the frequency of the signal handled by each circuit block divided by function is often different. For example, an FM tuner for Japan only has an RF signal of 76 to 9
0MHz, the intermediate frequency signal is 10.7MHz, and 2
Audio signals from 0 to 20,000Hz and 20Hz to 9
A wide range of signals of 0 MHz will be handled.

An example of the above FM/AM tuner is shown in FIG. In the figure, (1) is a mixing circuit (1) that receives FM broadcasting and mixes the received frequency signal with the oscillation frequency signal of the local oscillation circuit (2).
3) is an FM front-end circuit that converts the frequency into an intermediate frequency by mixing the intermediate frequency signal (I
The FM/IF amplification circuit that amplifies and limits the amplitude of the F-fold signal and detects it to obtain an FM stereo composite signal, 5) is a noise kiln having a function as described in Japanese Patent Publication No. 62-21461, for example. A cell circuit (6) is a multiplex circuit that demodulates Lf channel and R channel signals in the case of stereo broadcasting, and (7) is an AM tuner circuit that selects AM broadcasting and outputs an audio signal. For example, in the case of FM broadcast reception, the RF multiplied signal is input from the antenna (8), high frequency amplified by the RF amplifier circuit (9), and the oscillation frequency signal output by the local oscillation circuit (2) of the FM front end circuit (1) is FM front end circuit (
By mixing in the mixing circuit (3) of 1), an IF multiplied signal is output from the FM front end circuit (1>), and the IF multiplied signal is detected by the detection circuit of the FM/IF amplification circuit (4), thereby generating an FM-IF signal. The amplifier circuit (4) outputs a composite signal, and the multiplex circuit (6) outputs L channel and Rfw channel audio signals to the output terminal (10), respectively. F of
For example, the M tuner circuit was published on December 10, 1985,
It is described on page 152 of "'88 Sanyo Semiconductor Data Book: Bipolar Integrated Circuits for Portable Audio Edition".

Incidentally, electronic devices in recent years are required to be more and more compact and high-performance, and accordingly, the circuit shown in FIG. 6 is being made into a single chip as much as possible. However, in the example of the FM tuner mentioned above, the FM front end circuit (1) is several tens of M
Since it handles high frequency signals of Hz, interference with other circuits is likely to occur due to unnecessary radiation.

Furthermore, since a weak level signal from the antenna (8) is handled, the circuit operation tends to become unstable due to interference with other circuit blocks, and in severe cases, oscillation occurs. Therefore, FM
It was extremely difficult to integrate the front end circuit (1) into a single chip.

Furthermore, electronic devices in recent years have become increasingly diverse and diverse, and it is desired to shorten pattern design time. In addition, there are various demands such as deletion, replacement, or addition of specific circuit blocks to semiconductor integrated circuits whose designs have been completed. However, since the specific circuit blocks are not necessarily accommodated within the same occupied area, the design must be redesigned for each request, which has the disadvantage that it is not possible to immediately respond to the requests.

(c) Problems to be Solved by the Invention Mr. Otsuno, conventionally there was a drawback in that it was extremely difficult to integrate the FM front end circuit (1) as well, as circuit interference was likely to occur. In addition, the development period for the /< turn design was long, and it was not possible to quickly respond to various requests (there was one drawback).

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and the FM front-end circuit pro-nk (1) is covered with a shield electrode (17) that is electrically grounded. This solves the former problem. In addition, semiconductor chips (11
) is divided into mats (16) of substantially the same size, and each circuit block is accommodated in an area corresponding to an integer number of mats (16), thereby solving the latter problem.

(E) Function According to the present invention, the shield electrode (17
) can shield the FM front end circuit block (1), and also prevent interference with other circuits due to unnecessary radiation. Since each circuit block is accommodated in an area corresponding to an integer number of mats (16) of substantially the same size, it is possible to design each circuit block in parallel by considering the area for the integer number as one chip. Since the blocks are divided into a fixed number of elements and housed in each mat (16), it is also possible to design each mat (16). Therefore, pattern design time can be significantly shortened, and circuit changes can be made for each circuit block and each mat (16).

(f) Example Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a plan view showing a semiconductor integrated circuit according to the present invention. In the same figure, (11) is FM/AM as shown in Figure 6.
Semiconductor chip with tuner circuit integrated into one chip, (12)
is the power supply potential V. . (13) is the ground electrode pad/do for the ground potential GND, (14) is the power supply potential V. Power line for supplying C to each circuit, (1
5) is a ground line for supplying ground potential to each circuit, and 16) is a mat.

The mat (16) will be explained in detail later. And F.M.
-The IF amplifier circuit (4), multiplex circuit (6), etc. are housed in any area, and the FM front-end circuit (1) is placed on the same semiconductor chip (11) that houses them.
is stored, and a power supply potential VCC or ground potential GND, which is grounded in AC terms, is applied to the second part of the multilayer wiring structure.
A shield electrode (17) formed from the subsequent wiring layers is completely disposed to cover the area in which the FM front end circuit (1) is housed. Each circuit block is composed of circuit elements such as NPN or PNP I-transistors, resistors, and capacitors, and the functions of each circuit block are achieved by connecting these with electrode wiring.

In particular, if the connection wiring between the circuit elements is formed by the first layer wiring and the shield electrode is formed by the second layer wiring, the number of wiring layers can be minimized.

According to such a configuration, since the shield electrode (17) is fixed at a potential that is grounded in AC terms, the FM front end circuit (1), especially from the local oscillation circuit (2) that involves oscillation operation, is Unnecessary radiation can be shielded and interference with other circuits can be prevented.Also, since the shield electrode (17) can completely shield the FM front end circuit (1), interference from other circuits, especially at 10.7MHz, can be prevented. By preventing signal interference with the FM/IF amplifier circuit (4), which handles signals with similar frequencies and large amplitude levels, malfunctions such as oscillation can be prevented.

By the way, the FM front-end circuit (1) mainly consists of a local oscillation circuit (2) and a mixing circuit (3), and also includes an FM-IF amplifier circuit (3) that amplifies the IF output signal of the mixing circuit (3).
4) Amplification circuit for output to (IF-Atr+p>,
Other circuits associated with the main circuit are often incorporated, such as an automatic gain control circuit (AGC) for automatically controlling the received signal level. All of these circuits dislike interference with other circuits, especially the FM/IF amplifier circuit (4), but among them, the local oscillation circuit (2)
This is the circuit that requires the most attention, as it must accurately perform the highly unstable operation of high-frequency oscillation.

Therefore, as shown in FIG.
17) from having a common impedance, the shield electrode (17a) is firmly fixed to the alternating current ground potential, thereby stabilizing the circuit operation.

This is due to interference within the FM front end circuit (1) via the shield electrode (17) and interference current from other circuits reaching the local oscillation circuit (2) via the shield electrode (17). It also prevents interference. If the shield electrode (17b) covering the mixing circuit (3) and the shield electrode (17c) covering the other accompanying circuits are also divided into separate parts, the operation of the negative layer circuit can be stabilized.

In addition, in order to prevent mutual interference within the FM front end circuit (1), a ground electrode pad (13a) dedicated to the local oscillation circuit (2) is provided, and a ground line (15a) is also provided separately from the others. , interference caused by any of the ground potential GND wiring having a common impedance is prevented. The ground lines (15b) (15C) of the mixing circuit (3) and the other accompanying circuits are also extended individually and connected to the ground electrode pad 13b). At that time, the ground lines (15b) (15c) are connected by connecting the ground lines (15b) (15c) and the shield electrodes (17b) (17c) as close to the ground electrode pad (13b) as possible. Minimize unnecessary potential rise due to wiring impedance.

As mentioned above, the local oscillation circuit (2) is the circuit that requires the most attention, and is the circuit that is separated from the FM-IF amplifier circuit (4) as much as possible. Therefore, as shown in FIG. 1, the entire FM front-end circuit (1) is placed in the corner of the semiconductor chip (11), and as shown in FIG. By placing 2) at the farthest corner, the local oscillation circuit (2) can be
- Place it as far away from the IF amplifier circuit (4) as possible.

In this way, when the local oscillation circuit (2) is separated by a distance, the mixed circuit (3)
and the accompanying shield electrode for other circuits (17b
) (17c), signal interference from the FM/IF amplifier circuit (4) can be minimized. The separation to the corner also makes it possible to minimize the extension length of the ground line (15a) from the ground electrode pad (13a) to the local oscillation circuit (2), which contributes to stable operation of the local oscillation circuit (2). also contributes.

In FIG. 2, (18) is a suction electrode that makes ohmic contact with the high concentration separation region below. The suction electrode (18) is connected to a ground line (15c) extending between the local oscillation circuit (2> and mixing circuit (3) and the other associated circuits) to eliminate leakage current flowing between them. In addition to suction, NPN performs saturation operation in circuit elements.
-PNP: Provided in close proximity to circuit elements such as transistors, capacitors, and resistors that are expected to leak leakage current to suck out leakage current. The sucked leakage current is directly sucked out to the ground electrode pad (taa) (t3b) via the ground line (15c), or to the shield electrode (17a) (17b) (17c) that covers the circuit.
The shield electrodes (17a) (17b) (17
c) Ground line (15b) in contact with (15
c) Ground electrode pad (13a) via (15d)
(13b). Its cross-sectional structure is as shown in FIG.

In FIG. 3, (21) is a P-type semiconductor substrate, (22)
is an N-type epitaxial layer, (23) is an N4'-type buried region, (24) is a P+-type isolation region connected to the substrate (21),
(25) is an island for element formation, (26a) (26
b) is a dummy island, (27) and (28) are P or N type diffusion regions for forming circuit elements, (29) is an oxide film covering the epitaxial layer (22), and (30) is the first wiring layer. (15c) is the ground line, (18a) (18b) (18c) are the extraction electrodes, (3
1) is an interlayer insulating film, and (17a) and (17c) are shield electrodes formed by second layer wiring. Dummy Island (26
a) (26b) is the other circuit and the FM front end circuit (
This is provided to surround the entire FM front end circuit (1) in order to prevent interference due to leakage current with the FM front end circuit (1).
Furthermore, the dummy island (26b) is provided so as to surround only the local oscillation circuit (2) of the FM front end circuit (1). And some suction electrodes (18a)
(18b) extends the first wiring layer as it is to become the ground line (15d) (15c), and also connects the shield electrode (15c) through the through hole of the interlayer insulating film (31).
7a) Apply ground potential to (17c). Other suction electrodes (
18c) is connected to the shield electrode (17) via the through hole.
c), it is connected to the ground line (15c) via the shield electrode (17c).

In FIG. 2, only the local oscillation circuit (2) is connected to the ground line (15d) that applies the ground potential GND to the extraction electrode (18a) and the shield electrode (17a), and the circuit elements that constitute the local oscillation circuit (2). By separately providing a ground line (15a) for supplying the ground potential GND to the ground potential GND, the increase in the ground potential GND due to the leaked current can be suppressed and the circuit operation can be stabilized.

In addition, a lead pin for leading out to the outside is also provided exclusively.

According to the above configuration, the leak current flowing near the surface can be sucked out to the ground potential GND by the sucking electrode (18), so mutual interference with other circuits due to the leak current can be prevented. In addition, the extraction electrode (18) is not necessarily connected to the ground line (15), but is connected via the shield electrode (17), so the extraction electrode (18) is connected to the ground line (15) through the shield electrode (17). The electrode (18) can be placed so that the leakage current can be immediately sucked out in the immediate vicinity of the circuit element that is prone to leakage.

Hereinafter, a mat (16) that facilitates pattern design and a semiconductor integrated circuit in which the circuit shown in FIG. 6 is incorporated into the mat (16) will be described in detail.

In FIG. 4, first, a divided region (41) is formed at the center of the semiconductor chip (11) to cross it in a substantially straight line, and the element formation region of the semiconductor chip (11) is divided into two regions of substantially the same size above and below. compartmentalize. The divided area (41) is connected to the ground line (15) and power line (14) as described later.
) is a necessary and unavoidable region for extending a circuit element and does not form a circuit element, and by forming a divided region (41), the two divided regions are divided into first and second regions (41), respectively. 42) (43). Then, a division line (44) is provided in which a ground line (15) and a power supply line (14) are arranged as a pair and extend in a direction orthogonal to the division area line (41), and the division line (44) By arranging a plurality of matte marks 16) in parallel, the surface of the semiconductor chip (11) is divided into a large number of matte marks 16) of substantially the same size. The size of the mat (16) is set to an area that allows an arbitrary fixed number of elements to be laid out, and its width is empirically set to a width that allows five to six NPN I-Rangemetals to be arranged in one row.

On both sides of the mat (16), the ground line (15> and the power line (14) constituting the partition line (44) extend in pairs, so they are arranged regularly, for example, facing each other in a comb-like shape. By extending the mat (1
A ground line (15) and a power line (14) are extended on one side of the mat (6) and the power line (14) on the other side, respectively, to supply operating power to the circuit elements formed on the mat (16).

Ground line (15) extending the division line (44)
and power supply lines (14) are grouped together for each circuit block and depending on whether or not they are allowed to have a common impedance, and are extended over the divided area (41) to connect to the corresponding ground electrode pad (13). ) and power supply electrode pads (
12). As a result, a plurality of ground lines (15) and power lines (14) extend over the divided area (41), and each line is formed relatively wide to reduce wiring impedance. (41) also naturally requires a relatively large area.

The ground line (15) extending the division line (44)
) and the power supply line (14), the ground line (15) and the power supply line (14) extending over the divided area (41), and the connection wiring between the circuit elements in each mat (16) are arranged in a comb-shaped layout. This is basically done using the first wiring layer. From the second layer onwards, the plot line (44
) and divided areas (41) to form signal transmission wiring between mats (16) and shield electrodes (17).

In addition, the division area (41) is sometimes divided into each division line (44).
Also extend parallel to. This is due to positional constraints of the VCC electrode pad (12) and ground electrode pad (13) in response to package bin arrangement requirements, and adjacent mats (13).
6) Or, if there is a relationship that particularly requires separation in circuit functional blocks, it is provided between each mat (16). In Figure 4, the reason for the former is between mats D and E, and mat M
The reason for the latter is between and N. Then, from the VCC electrode pad (12) and ground pad (13) provided near the end of the divided region (41a) extending in parallel,
The cc line (14) and the ground line (15) are routed, and then routed over the divided area (41) that crosses the center of the semiconductor chip (11) to connect to the circuit elements in each mat (16). .

When functional circuit blocks are housed in a semiconductor chip (11) in which the element formation area is divided into a large number of mats (16) in this way, each circuit block is housed as follows.

First, since the mat (16) is designed to have a size that can accommodate an arbitrary fixed number of elements, the circuit block is divided into the fixed number of elements. For example, the size of Matsu L-(16) is for accommodating 100 elements, and the circuit block has 270 elements.
If the number of mats is about 100 elements, prepare three mats (16) and divide each mat into 100 elements. Of course, capacitors, etc. that occupy a large area should be taken into consideration. Then, the circuit elements are stored in each mat (16) according to the above classification, and the circuit elements are stored in each mat (16).
16) Connection wiring between circuit elements such as NPN-PNP transistors, diodes, resistors, and capacitors housed in the first wiring layer is terminated at the first wiring layer. After repeating this process and completing the pattern design for all the mats (16), the three mats (16) are arranged adjacently, and the electrical connection between each mat (16) is established by wiring from the second layer onwards. By making connections, functional circuit blocks are configured. After all the circuit blocks are housed in the mat (16), all the mats (16) are combined and electrical connections are made between each circuit block using the second and subsequent wiring layers to form the entire IC. design.

The above method also applies when storing the FM front end circuit (1) of the present application. In other words, the FM front end circuit (1
) consists of about 250 elements, so prepare three mats (16) and divide the entire FM front-end circuit (1) into 80 to 100 elements, and according to this division mat) K ,L.

A circuit element is housed in each M, and connection wiring is arranged. Then, place a shield electrode (1
7) is provided, and a ground potential GND is applied through ground electrode pads (13a) (13b) provided exclusively for the FM front end circuit (1). The other circuit blocks are also housed in an integral number of mats (16) according to the above method.

According to such a configuration, each circuit block is formed by an integer number of mats (
16), it becomes possible to design each circuit block and to divide the circuit block into a fixed number of elements to design each mat (16). Therefore, it is possible to design each circuit block in parallel, and the design period can be significantly shortened. Therefore, by storing the FM front end circuit (1) in the mat (16), a semiconductor integrated circuit incorporating the FM front end circuit (1) can be designed in a short period of time, and by providing the shield electrode (17), mutual interference can be prevented and the FM
The M front end circuit (1) can be integrated into one chip. Further, since circuit changes can be made for each circuit block and each mat, there is no need to change the design of the entire IC.

By the way, the ground line (15) and power line (14)
) in the first wiring layer and the shield electrode (17) in the second wiring layer, because there is a partition line (44), the mat (1) in the FM front end circuit (1)
6) The degree of freedom in designing the connection wiring between the two is limited.

Therefore, the FM front end circuit (1) is connected to the division line (
44), the entire structure can be completed with a two-layer wiring structure.

This will be explained again using FIGS. 1 and 2.

That is, as is clear from the overall plan view in FIG. 1 and the partially enlarged plan view in FIG. By arbitrarily extending the power supply line (14) and using the second layer wiring from around the shield electrode (17), the connection between the FM front end circuit 1> and the mat (16) constituting other circuits is achieved. Perform connection wiring. F
The pattern layout in the FM front-end circuit (1) should be in accordance with Figure 2, and in order to facilitate relocation, the area occupied by the FM front-end circuit (1) should be equal to an integer number of mats (16), specifically, It can be stored within an area approximately equal to three pieces. With this configuration, there is no division line (44) in the FM front end circuit (1), so the degree of freedom in wiring design is increased, and the shield electrode (17)
It is possible to efficiently incorporate the FM front end circuit (1) provided with the above.

Particularly when the number of mats (16) increases, the divided areas (41
), it is essential to make the mat (16) a multi-stage structure, so the FM front end circuit (1
) is stored in mat (16) regardless of whether it is stored in mat (16) or not.
16) By arranging a large number of mats (16) in an area approximately equal to an integer number, it becomes easy to arrange a large number of mats (16) in a rectangular shape.

The divided area (41) requires a relatively large occupied area=2
3. Therefore, by arranging a circuit block that is likely to cause interference with the FM front end circuit (1) across the divided area (41), it is easy to separate the two in terms of distance. Or in Figure 4, on the mat ~
FM-IF has the function of forming an FM front end circuit (1) in the corner of the semiconductor chip (11) by using the space between the mats, and amplifying and limiting the amplitude of this output signal using an IF multiplier signal limiter amplifier circuit. The amplifier circuit (4) utilizes the mats E to I, and forms both mats with a divided region (41) in between. Furthermore, the AM tuner circuit (7) is connected to mat A to mat D, the noise cancellation circuit (5) is connected to mat N to mat P, the multiplex decoder circuit (6) is connected to mat Q to mat T, and others (optional). The circuits are respectively integrated on the mat I.

The layout within the FM front end circuit (1) may be similar to that shown in FIG.

According to such a configuration, the FM treated with the shield electrode (17)
F that requires the most attention for the front end circuit (1)
Since the M-IF amplifier circuit (4) can be placed apart from the divided region (41), the effect of the shield electrode 17) can be maximized. Furthermore, according to the arrangement shown in FIG. 1, the FM front end circuit (1) is divided into divided regions (41>(
41a) and the ground line (15), a fixed potential wiring is extended between the two, which can contribute to preventing interference due to radiation between the two.

FIG. 5 shows an FM/AM receiver constructed using an IC that also incorporates the FM front end circuit (1). In the same figure, (50) is a mixing circuit (
3) or a tuning circuit that outputs to the mixing circuit of the AM tuner circuit (7), (51) and (52) are surface acoustic wave filters (
53) from the output signal of the mixing circuit (3).
The first step is to extract the IF multiplied signal. second filter circuit, (54
) is the passive circuit element of the local oscillation circuit (2) that determines the oscillation frequency of the FM/local oscillation circuit (2), and (55) is the voltage controlled oscillation circuit (VC) of the multiplex decoder circuit (6).
A crystal oscillator that determines the oscillation frequency of O), (56) is A
Filter circuit for passing M-IF multiplied signal (57)
is a passive circuit element of the local oscillation circuit of the AM tuner circuit (7), and (58) is the output terminal of the L and R channel.

In addition, capacitors and resistors whose element constants are difficult to integrate are externally attached to realize the entire circuit.

According to the above configuration, the FM/
Since an AM tuner can be realized, an inexpensive tuner can be constructed by reducing the number of parts.

()) As described in detail, according to the present invention, the shield electrode (17)
By providing this, unnecessary radiation and other interference can be prevented, so there is an advantage that the 2M7028121 circuit (1) can also be integrated in the same chip (11).

In addition, the shield electrode (17
) is divided, which has the advantage of preventing signal interference to the local oscillation circuit <2) via the shield electrode (17).

Furthermore, since the local oscillation circuit (2) of the 2M7028121 circuit (1) is placed in the corner of the semiconductor chip (11), the local oscillation circuit (2) can be positioned as far away from other circuits as possible. This has the advantage of minimizing the effects of mutual interference.

Since the extraction electrode (18) in the 2M7028121 circuit (1) is connected to the ground line (15) via the shield electrode (17), there is an advantage that the extraction electrode (18) can be placed at any position.

Next, for ICs made using mats (16), patterns can be designed for each mat (16), and the entire IC layout can be created by combining the designed mats (16). It has the advantage that an IC including the circuit (1>) can be easily designed, and the shield electrode (17) can prevent mutual interference and facilitate coexistence.

At that time, by removing the partition line (44) in the 2M7028121 circuit (1), the shield electrode (17) can be formed without impairing the degree of freedom in wiring design with two-layer wiring, and the occupied area can be reduced to a mat ( 16) Since there are an integral number of mats (16), there is an advantage that the mats (16) can be easily arranged and relocated.

In addition, by providing the divided area (41) and making the mat (16) a multi-stage structure, the 2M7028121 circuit (1)
A large number of mats (16) can be stored in a square shape, and the 2M7028121 circuit (1) is
Since the mats (16) are formed in an integral number of areas, the mats (16) have the advantage of being easy to arrange and combine.

Furthermore, 2M7028121 with the divided area (41) in between
By arranging the circuit (1) and the FM-IF amplifier circuit (4), they can be separated by the division area (41) and surrounded by the ground line (15), so that the radiation and other effects of both can be reduced. This has the advantage of minimizing interference caused by

Furthermore, since the semiconductor integrated circuit described above can also incorporate the 2M7028121 circuit (1) into a single chip, passive circuit elements such as capacitors, resistors, and varistors, which are difficult to integrate in terms of value, and circuit elements constituting the tuned circuit can be combined. By adding
This has the advantage that an inexpensive and high-performance FM/AM tuner can be constructed.

[Brief explanation of the drawing]

Figure 1 is a plan view for explaining the present invention, Figure 2 is a 2M7
028121 A partially enlarged plan view of the circuit (1) part, FIG. 3 is a sectional view of the main part of FIG. 2, FIG. 4 is a plan view for explaining the present invention in detail, and FIG. 5 is a radio reception of the present invention. FIG. 6 is a circuit diagram showing the FM/AM tuner circuit. (1) is the FM front-end circuit, (2) is the local oscillation circuit, (4) is the FM-IF amplifier circuit, (11) is the semiconductor chip, (14) is the power supply line, (15) is the ground line, (16) is the ) is a mat, (17) is a shield electrode, (18) is a suction electrode, (41) is a dividing area, (44) is a division line, and (50) is a tuning circuit.

Claims (11)

[Claims] (1) Includes at least a local oscillation circuit and a mixing circuit
A front-end circuit block that converts a radio frequency signal into an IF (intermediate frequency) signal and an IF amplification circuit block that amplifies and limits the amplitude of the IF signal are integrated on the same semiconductor substrate, and the front-end circuit block is integrated on the same semiconductor substrate. A semiconductor integrated circuit characterized in that the top is covered with a shield electrode grounded in an alternating current manner. (2) The semiconductor integrated circuit according to claim 1, wherein the shield electrode is formed of a second wiring layer. (3) The shield electrode is divided into a shield electrode that covers the local oscillation circuit and one or more shield electrodes that cover other circuits of the front-end circuit block. The semiconductor integrated circuit described in . (4) The semiconductor integrated circuit according to claim 1, wherein the local oscillation circuit is arranged at a corner of the semiconductor chip. (5) A suction electrode is provided in the front-end circuit block to make ohmic contact with a high concentration isolation region connected to a semiconductor substrate, and is connected to a ground electrode pad via the shield electrode. 1
The semiconductor integrated circuit described in . (6) By dividing the semiconductor chip into a plurality of regions of substantially the same size by arranging a plurality of division lines in parallel on the surface of the semiconductor chip, each of which has a power supply line and a ground line extending in pairs. The area is a mat, front-end circuit blocks having at least a local oscillation circuit are formed in an area approximately equal to the area of an integer number of mats, and a plurality of circuit blocks having different functions from the front-end circuit blocks are each formed in an integer number of areas. A semiconductor integrated circuit, characterized in that the semiconductor integrated circuit is housed in a mat, the surface of the front end circuit block is covered with a shield electrode, and the shield electrode is grounded in an alternating current manner. (7) The power supply line, the ground line, and the connection wiring within the mat are formed in a first wiring layer, and the connection wiring between mats and circuit blocks, and the shield electrode are formed in a second layer. 7. The semiconductor integrated circuit according to claim 6, wherein the semiconductor integrated circuit is formed of a wiring layer. (8) The semiconductor chip is divided into first and second regions by a dividing region extending in a substantially straight line through the center of the semiconductor chip, and a power supply line and a ground line are extended in pairs in a direction perpendicular to the dividing region. The first and second areas are divided into a plurality of areas of substantially the same size by arranging a plurality of partition lines in parallel, each area is made into a mat, and each area is individually marked on the divided area. A power supply or ground line connected to the electrode pad is extended to the mat, and a front-end circuit block including at least a local oscillation circuit is formed in an area approximately equal to the area of an integral number of mats, and the front-end circuit has a function 1. A semiconductor integrated circuit characterized in that a plurality of different circuit blocks are housed in an integral number of mats, and the surface of the front-end circuit block is covered with a shield electrode grounded in an alternating current manner. (9) A power supply line and a ground line constituting the division line, a power supply line and a ground line extending over the division area, and connection wiring within the mat are formed by first layer wiring, and the mats are connected to each other. 9. The semiconductor integrated circuit according to claim 8, wherein the connection electrode between the circuit blocks, the connection electrode between the circuit blocks, and the shield electrode are formed of second layer wiring. (10) The local oscillation circuit of the front-end circuit block is placed in a corner of the semiconductor chip, and the IF (intermediate frequency) signal output from the front-end circuit block is placed diagonally across the semiconductor chip, sandwiching the divided area. 9. The semiconductor integrated circuit according to claim 8, further comprising an IF amplifier circuit block for amplifying and limiting amplitude. (11) A radio receiver characterized in that external parts are added to the semiconductor integrated circuit according to claim 1, 6, or 8.