JPH03101520U - - Google Patents
Info
- Publication number
- JPH03101520U JPH03101520U JP1990009528U JP952890U JPH03101520U JP H03101520 U JPH03101520 U JP H03101520U JP 1990009528 U JP1990009528 U JP 1990009528U JP 952890 U JP952890 U JP 952890U JP H03101520 U JPH03101520 U JP H03101520U
- Authority
- JP
- Japan
- Prior art keywords
- film
- integrated circuit
- circuit board
- layer
- silver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Die Bonding (AREA)
Description
第１図は本考案の一実施例の縦断面図、第２図
は本実施例におけるベア・チツプ搭載後の縦断面
図である。 １……誘電体基板、２……第１層導体膜、３…
…第２層導体膜、４……ベア・チツプ、５……合
金層、６……ワイヤボンデイング箇所。
は本実施例におけるベア・チツプ搭載後の縦断面
図である。 １……誘電体基板、２……第１層導体膜、３…
…第２層導体膜、４……ベア・チツプ、５……合
金層、６……ワイヤボンデイング箇所。
Claims (1)
- 【実用新案登録請求の範囲】 １ ベア・チツプを基板上に搭載してワイヤボン
デイング作業を必要とする厚膜集積回路基板にお
いて、前記ベア・チツプの搭載部が銀／パラジユ
ーム膜からなる第１層導体膜と金膜からなる第２
層導体膜の２層構造で形成されていることを特徴
とする厚膜集積回路基板。 ２ 前記第１層導体膜が銀／白金膜にて形成され
ていることを特徴とする請求項１記載の厚膜集積
回路基板。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990009528U JPH03101520U (ja) | 1990-01-31 | 1990-01-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990009528U JPH03101520U (ja) | 1990-01-31 | 1990-01-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03101520U true JPH03101520U (ja) | 1991-10-23 |
Family
ID=31513127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990009528U Pending JPH03101520U (ja) | 1990-01-31 | 1990-01-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03101520U (ja) |
-
1990
- 1990-01-31 JP JP1990009528U patent/JPH03101520U/ja active Pending