JPH03107805U

JPH03107805U -

Info

Publication number: JPH03107805U
Application number: JP6300190U
Authority: JP
Priority date: 1989-12-05
Filing date: 1990-06-14
Publication date: 1991-11-06

Description

[Brief explanation of drawings]

第１図は本考案第１の実施例を説明する図、第
２図は本考案第２の実施例を説明する図、第３図
は従来のパツケージの高周波等価回路図、第４図
は従来のパツケージを説明する図である。４ｂ……第１の接地電極端子、４ｃ……第２の
接地電極端子、４ｅ……接続電極、５ｂ……入力
電極端子、６ｂ……出力電極端子、７……キヤビ
テイ、１１，１２，１３……ボンデイングワイヤ
ー、７０……凹状の切り欠き、１００……側壁メ
タライズ。 Figure 1 is a diagram explaining the first embodiment of the present invention, Figure 2 is a diagram explaining the second embodiment of the present invention, Figure 3 is a high frequency equivalent circuit diagram of a conventional package, and Figure 4 is a diagram of the conventional package. It is a figure explaining the package of. 4b...First ground electrode terminal, 4c...Second ground electrode terminal, 4e...Connection electrode, 5b...Input electrode terminal, 6b...Output electrode terminal, 7...Cavity, 11, 12, 13 ... Bonding wire, 70 ... Concave notch, 100 ... Side wall metallization.

Claims

[Claims for Utility Model Registration] 1. A semiconductor device packaging system having a cavity structure, which has a first ground electrode terminal, an input electrode terminal, and an output electrode terminal on the surface of the stem, and a second ground electrode terminal on the bottom surface of the cavity. It has a ground electrode terminal, the depth of the cavity is approximately the same as the thickness of the semiconductor device chip to be mounted, and the first and second ground electrode terminals are electrically connected. Semiconductor device packaging stem. 2. The semiconductor device packaging stem according to claim 1, wherein the cavity is formed in a concave manner between the electrode terminals on the surface of the stem.