JPH03128939U - - Google Patents

Info

Publication number
JPH03128939U
JPH03128939U JP1990037339U JP3733990U JPH03128939U JP H03128939 U JPH03128939 U JP H03128939U JP 1990037339 U JP1990037339 U JP 1990037339U JP 3733990 U JP3733990 U JP 3733990U JP H03128939 U JPH03128939 U JP H03128939U
Authority
JP
Japan
Prior art keywords
main body
integrated circuit
view
section
circuit section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990037339U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990037339U priority Critical patent/JPH03128939U/ja
Publication of JPH03128939U publication Critical patent/JPH03128939U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図〜第１４図は本考案の実施例を示してお
り、第１図はこの実施例に係る半導体装置の部分
斜視図、第２図は第１図の−面断面図、第３
図Ａ〜Ｉはこの半導体装置の製造工程を示す工程
説明図、第４図はこの製造工程における外側本体
群搭載基体の斜視図、第５図は第４図の部分拡大
図、第６図Ａは外側本体の一部拡大斜視図、第６
図Ｂは内側本体チツプの一部拡大斜視図、第７図
は外側本体の嵌込部に内側本体チツプを嵌込んだ
状態を一部拡大斜視図、第８図は外側本体と内側
本体チツプの隙間部にガラス・ペーストを充填し
た状態の拡大斜視図、第９図はフオトリゾグラフ
イー工程とエツチング工程を経てボンデイングパ
ツドと配線部とが形成された状態の一部拡大斜視
図、第１０図は得られた半導体装置の一部拡大斜
視図、第１１図Ａ〜Ｂは接続素子部として粗回路
を備える外側本体とこの嵌込部に嵌込まれる内側
本体チツプの一部拡大斜視図、第１２図Ａ〜Ｂは
実施例に係る外側本体の説明図、第１３図及び第
１４図は変形例に係る外側本体の説明図をそれぞ
れ示し、また、第１５図〜第１８図は従来例を示
し、第１５図は従来の半導体装置の部分拡大斜視
図、第１６図〜第１８図はその製造工程を示す概
略斜視図である。 符号説明、１……外側本体、２……内側本体チ
ツプ、３……充填部、１０……嵌込部、１１……
ボンデイングパツド、２０……集積回路部。

Claims (1)

  1. 【実用新案登録請求の範囲】 基板上に設けられた複数の半導体素子群より形
    成された集積回路部と、 この集積回路部周縁の基板上に設けられ上記集
    積回路部に接続された接続素子部とを備える半導
    体装置において、 上記集積回路部が搭載された内側本体と、 この内側本体を嵌込むための嵌込部を備え上記
    接続素子部が搭載された外側本体とに分割し、 かつ、上記外側本体とこの嵌込部に嵌込まれた
    内側本体との隙間部に絶縁材料を充填して外側本
    体と内側本体とを一体化したことを特徴とする半
    導体装置。
JP1990037339U 1990-04-09 1990-04-09 Pending JPH03128939U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990037339U JPH03128939U (ja) 1990-04-09 1990-04-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990037339U JPH03128939U (ja) 1990-04-09 1990-04-09

Publications (1)

Publication Number Publication Date
JPH03128939U true JPH03128939U (ja) 1991-12-25

Family

ID=31544358

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990037339U Pending JPH03128939U (ja) 1990-04-09 1990-04-09

Country Status (1)

Country Link
JP (1) JPH03128939U (ja)

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