JPH03255657A - 混成集積回路装置 - Google Patents

混成集積回路装置

Info

Publication number
JPH03255657A
JPH03255657A JP2054119A JP5411990A JPH03255657A JP H03255657 A JPH03255657 A JP H03255657A JP 2054119 A JP2054119 A JP 2054119A JP 5411990 A JP5411990 A JP 5411990A JP H03255657 A JPH03255657 A JP H03255657A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
hybrid integrated
chips
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2054119A
Other languages
English (en)
Inventor
Akio Koyanagi
小柳　昭夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2054119A priority Critical patent/JPH03255657A/ja
Publication of JPH03255657A publication Critical patent/JPH03255657A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路装置に関し、特に２つの重なって
いるＩＣチップを実装した混成集積回路装置に関する。
〔従来の技術〕
従来の混成集積回路装置は、第２図に示すように、基板
１上に２個のＩＣチップ３を横に並べて同一平面上にマ
ウン１−　Ｌ、ＩＣチップ３のメタライズ電極１２と基
板上のメタライズ電１２を金線４で電気的に接続して実
装されていた。
〔発明が解決しようとする課題〕
上述した従来の２個のＩＣチップを基板上に実装する方
法としては、第２図に示すように、ＩＣチップ３を横に
並べて同一平面上に実装されていた。
しかしながら、ＩＣチップ３２個分のスペースが基板１
上に必要になり、実装面積の低減をはかるには限界があ
った。
本発明の目的は、実装面積の低減により、高密度実装が
可能な混成集積回路装置を提供することにある。
〔課題を解決するための手段〕
本発明は、ＩＣチップを実装した混成集積回路装置にお
いて、２個の前記ＩＣチップのそれぞれの裏面を重ねて
一方の前記ＩＣチップをフリップチップ接続と、他方の
前記ＩＣチップをワイヤーボンディング接続を用い実装
されている。
〔実施例〕
次に、本発明の実施例について図面を参照して説明する
。
第１図は本発明の一実施例の断面図である。
第１図に示すように、基板１上に、２個のＩＣチップ３
のそれぞれの裏面を非導電性接着剤５により接続し、一
方をフリップチップ接続を用いて基板１上のメタライズ
電極２とＩＣチップ上に形成されたメタライズ電極１２
をバンプ６により電気的に接続し、他方をワイヤーボン
ディング接続を用いてメタライズ電！２．１２を金線４
により電気的に接続し、基板１上に実装されている。
〔発明の効果〕
以上説明したように本発明は、一方をフリップチップ接
続と他方をワイヤーボンディング接続を用いて、２個の
ＩＣチップのそれぞれの裏面を重ねて基板上に実装する
ことにより部品搭載を高密度化できる効果がある。
【図面の簡単な説明】
第１図は本発明の一実施例の断面図、第２図は従来の混
成集積回路装置の１例の断面図である。 １・・・基板、２．１２・・・メタライズ電極、３・・
・ＩＣチップ、４・・・金線、５・・・非導電性接着剤
、６・・・バンプ。

Claims (1)

    【特許請求の範囲】
  1. ＩＣチップを実装した混成集積回路装置において、２個
    の前記ＩＣチップのそれぞれの裏面を重ねて一方の前記
    ＩＣチップをフリップチップ接続と、他方の前記ＩＣチ
    ップをワイヤーボンディング接続を用い実装することを
    特徴とする混成集積回路装置。
JP2054119A 1990-03-05 1990-03-05 混成集積回路装置 Pending JPH03255657A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2054119A JPH03255657A (ja) 1990-03-05 1990-03-05 混成集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2054119A JPH03255657A (ja) 1990-03-05 1990-03-05 混成集積回路装置

Publications (1)

Publication Number Publication Date
JPH03255657A true JPH03255657A (ja) 1991-11-14

Family

ID=12961712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2054119A Pending JPH03255657A (ja) 1990-03-05 1990-03-05 混成集積回路装置

Country Status (1)

Country Link
JP (1) JPH03255657A (ja)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327325A (en) * 1993-02-08 1994-07-05 Fairchild Space And Defense Corporation Three-dimensional integrated circuit package
WO1996017505A1 (en) * 1994-12-01 1996-06-06 Motorola Inc. Method, flip-chip module, and communicator for providing three-dimensional package
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US5767570A (en) * 1993-03-18 1998-06-16 Lsi Logic Corporation Semiconductor packages for high I/O semiconductor dies
US5815372A (en) * 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
WO2001037332A1 (en) * 1999-11-16 2001-05-25 Indian Space Research Organisation A high density hybrid integrated circuit package having a flip-con structure
KR20020016278A (ko) * 2000-08-25 2002-03-04 듀흐 마리 에스. 플립 칩 기술 공정에서 개량된 칩 실장 방법
US6452279B2 (en) 2000-07-14 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US7015063B2 (en) 1998-03-31 2006-03-21 Micron Technology, Inc. Methods of utilizing a back to back semiconductor device module
US7906852B2 (en) 2006-12-20 2011-03-15 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method of the same

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327325A (en) * 1993-02-08 1994-07-05 Fairchild Space And Defense Corporation Three-dimensional integrated circuit package
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US5767570A (en) * 1993-03-18 1998-06-16 Lsi Logic Corporation Semiconductor packages for high I/O semiconductor dies
WO1996017505A1 (en) * 1994-12-01 1996-06-06 Motorola Inc. Method, flip-chip module, and communicator for providing three-dimensional package
US6337227B1 (en) 1996-02-20 2002-01-08 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US6165815A (en) * 1996-02-20 2000-12-26 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6989285B2 (en) 1996-05-20 2006-01-24 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US7371612B2 (en) 1996-05-20 2008-05-13 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US5815372A (en) * 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US7015063B2 (en) 1998-03-31 2006-03-21 Micron Technology, Inc. Methods of utilizing a back to back semiconductor device module
US7057291B2 (en) * 1998-03-31 2006-06-06 Micron Technology, Inc. Methods for securing vertically mountable semiconductor devices in back-to back relation
US7282789B2 (en) 1998-03-31 2007-10-16 Micron Technology, Inc. Back-to-back semiconductor device assemblies
WO2001037332A1 (en) * 1999-11-16 2001-05-25 Indian Space Research Organisation A high density hybrid integrated circuit package having a flip-con structure
US6452279B2 (en) 2000-07-14 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
KR20020016278A (ko) * 2000-08-25 2002-03-04 듀흐 마리 에스. 플립 칩 기술 공정에서 개량된 칩 실장 방법
US7906852B2 (en) 2006-12-20 2011-03-15 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method of the same

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