JPH0367450U - - Google Patents
Info
- Publication number
- JPH0367450U JPH0367450U JP1989128861U JP12886189U JPH0367450U JP H0367450 U JPH0367450 U JP H0367450U JP 1989128861 U JP1989128861 U JP 1989128861U JP 12886189 U JP12886189 U JP 12886189U JP H0367450 U JPH0367450 U JP H0367450U
- Authority
- JP
- Japan
- Prior art keywords
- inner lead
- lead
- semiconductor element
- tip
- thin metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図はこの考案の一実施例による半導体装置
用リードフレームに半導体素子を搭載し金属細線
で結線した状態の部分平面図、第２図は第１図の
−線における断面図、第３図は第１図の部
の拡大斜視図、第４図及び第５図は従来の半導体
装置用リードフレームの部分平面図である。 １……半導体素子、２……ダイスパツド、３…
…電極、４……金属細線、５……インナーリード
、６……絶縁体。なお、図中、同一符号は同一、
または相当部分を示す。
用リードフレームに半導体素子を搭載し金属細線
で結線した状態の部分平面図、第２図は第１図の
−線における断面図、第３図は第１図の部
の拡大斜視図、第４図及び第５図は従来の半導体
装置用リードフレームの部分平面図である。 １……半導体素子、２……ダイスパツド、３…
…電極、４……金属細線、５……インナーリード
、６……絶縁体。なお、図中、同一符号は同一、
または相当部分を示す。
Claims (1)
- 半導体素子を搭載するためのダイスパツドと半
導体素子上に形成された電極と金属細線にて結線
することにより外部へ信号を取り出すインナーリ
ードとを備えたリードフレームにおいて、インナ
ーリード先端部の金属細線を接合する領域を囲む
形でインナーリード先端と両端に連続してインナ
ーリード上に絶縁体を形成したことを特徴とする
半導体装置用リードフレーム。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989128861U JPH0367450U (ja) | 1989-11-01 | 1989-11-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989128861U JPH0367450U (ja) | 1989-11-01 | 1989-11-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0367450U true JPH0367450U (ja) | 1991-07-01 |
Family
ID=31676535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989128861U Pending JPH0367450U (ja) | 1989-11-01 | 1989-11-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0367450U (ja) |
-
1989
- 1989-11-01 JP JP1989128861U patent/JPH0367450U/ja active Pending