JPS63174459U - - Google Patents
Info
- Publication number
- JPS63174459U JPS63174459U JP1987049157U JP4915787U JPS63174459U JP S63174459 U JPS63174459 U JP S63174459U JP 1987049157 U JP1987049157 U JP 1987049157U JP 4915787 U JP4915787 U JP 4915787U JP S63174459 U JPS63174459 U JP S63174459U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- mounting surface
- lead wire
- wire tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は、本考案に係る半導体装置の要部切欠
上面図、第２図は、第１図に示す半導体装置の側
断面図、第３図は、従来の半導体装置の側断面図
である。 １１……基板、１２……素子、１３……リード
線、１４……ワイヤ、１５……樹脂、１７……膨
出部。
上面図、第２図は、第１図に示す半導体装置の側
断面図、第３図は、従来の半導体装置の側断面図
である。 １１……基板、１２……素子、１３……リード
線、１４……ワイヤ、１５……樹脂、１７……膨
出部。
Claims (1)
- 基板と、基板に取付けた素子と、外部に導出す
るリード線先端と、リード線先端と素子の電極を
結線したワイヤを、樹脂で埋設封止した半導体装
置において、前記基板の素子取付面をプレスして
、素子取付面の裏面に膨出部を形成したことを特
徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987049157U JPS63174459U (ja) | 1987-03-31 | 1987-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987049157U JPS63174459U (ja) | 1987-03-31 | 1987-03-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63174459U true JPS63174459U (ja) | 1988-11-11 |
Family
ID=30871347
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987049157U Pending JPS63174459U (ja) | 1987-03-31 | 1987-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63174459U (ja) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5622382A (en) * | 1979-05-09 | 1981-03-02 | Herko Pyrolyse Recycling | Waste decompositin method and apparatus |
| JPS5731300A (en) * | 1980-06-20 | 1982-02-19 | Pioneer Electronic Corp | Matrix circuit |
-
1987
- 1987-03-31 JP JP1987049157U patent/JPS63174459U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5622382A (en) * | 1979-05-09 | 1981-03-02 | Herko Pyrolyse Recycling | Waste decompositin method and apparatus |
| JPS5731300A (en) * | 1980-06-20 | 1982-02-19 | Pioneer Electronic Corp | Matrix circuit |