JPH0434747U - - Google Patents

Info

Publication number
JPH0434747U
JPH0434747U JP1990075655U JP7565590U JPH0434747U JP H0434747 U JPH0434747 U JP H0434747U JP 1990075655 U JP1990075655 U JP 1990075655U JP 7565590 U JP7565590 U JP 7565590U JP H0434747 U JPH0434747 U JP H0434747U
Authority
JP
Japan
Prior art keywords
container
weight
parts
lead terminal
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1990075655U
Other languages
English (en)
Other versions
JP2518721Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990075655U priority Critical patent/JP2518721Y2/ja
Publication of JPH0434747U publication Critical patent/JPH0434747U/ja
Application granted granted Critical
Publication of JP2518721Y2 publication Critical patent/JP2518721Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案の半導体素子収納用パツケージ
の一実施例を示す断面図である。 １……絶縁基体、２……蓋体、３……容器、５
……外部リード端子、６ａ，６ｂ……有機樹脂接
着材。

Claims (1)

    【実用新案登録請求の範囲】
  1. 絶縁基体と蓋体とから成り、内部に半導体素子
    を収容するための空所を有する容器と、該容器内
    に収容される半導体素子を外部電気回路に電気的
    に接続するための外部リード端子とから成る半導
    体素子収納用パツケージにおいて、前記外部リー
    ド端子を容器に、エポキシ樹脂１００重量部に対
    し２０乃至１６０重量部の無機物充填剤を添加し
    て成る有機樹脂接着剤を介して取着固定したこと
    を特徴とする半導体素子収納用パツケージ。
JP1990075655U 1990-07-16 1990-07-16 半導体素子収納用パッケージ Expired - Lifetime JP2518721Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990075655U JP2518721Y2 (ja) 1990-07-16 1990-07-16 半導体素子収納用パッケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990075655U JP2518721Y2 (ja) 1990-07-16 1990-07-16 半導体素子収納用パッケージ

Publications (2)

Publication Number Publication Date
JPH0434747U true JPH0434747U (ja) 1992-03-23
JP2518721Y2 JP2518721Y2 (ja) 1996-11-27

Family

ID=31616422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990075655U Expired - Lifetime JP2518721Y2 (ja) 1990-07-16 1990-07-16 半導体素子収納用パッケージ

Country Status (1)

Country Link
JP (1) JP2518721Y2 (ja)

Also Published As

Publication number Publication date
JP2518721Y2 (ja) 1996-11-27

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term