JPH0446492U - - Google Patents
Info
- Publication number
- JPH0446492U JPH0446492U JP8884990U JP8884990U JPH0446492U JP H0446492 U JPH0446492 U JP H0446492U JP 8884990 U JP8884990 U JP 8884990U JP 8884990 U JP8884990 U JP 8884990U JP H0446492 U JPH0446492 U JP H0446492U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- synchronization signal
- output
- input
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002131 composite material Substances 0.000 claims description 4
- 238000000926 separation method Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims 1
- 230000001960 triggered effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
- Details Of Television Scanning (AREA)
Description
第１図は本考案の一実施例を示すＥＤＴＶ等の
倍速処理回路のブロツク図、第２図は同第１図中
のマスキング回路のブロツク図、第３図は同第２
図を説明するためのタイミングチヤート、第４図
は従来の倍速処理回路のブロツク図、第５図は同
第４図を説明するためのタイミングチヤートであ
る。
１は同期分離回路、２はマスキング回路、３は
フリツプフロツプ４、ナンドゲート回路５等から
なる1/2の分周器、６は位相検出回路７、電圧制
御発振器９、水平ドライブカウンタ１０、偏向回
路１１出力のＡＦＣパルス１３等からなるＡＦＣ
ループ回路、１４はカウンタ、１５はパルスの立
ち下がりでトリガするＲＳ−フリツプフロツプ、
１６はインバータ回路、１７はオアゲート回路、
１８は倍速のコンポジツト信号、Ａは分離後のコ
ンポジツト同期信号、ＶＤは垂直同期信号、Ｅは
マスキングした水平同期信号である。
Fig. 1 is a block diagram of a double speed processing circuit such as an EDTV showing an embodiment of the present invention, Fig. 2 is a block diagram of a masking circuit in Fig. 1, and Fig. 3 is a block diagram of a masking circuit in Fig.
FIG. 4 is a block diagram of a conventional double speed processing circuit, and FIG. 5 is a timing chart for explaining FIG. 4. 1 is a synchronous separation circuit, 2 is a masking circuit, 3 is a 1/2 frequency divider consisting of a flip-flop 4, a NAND gate circuit 5, etc., 6 is a phase detection circuit 7, a voltage controlled oscillator 9, a horizontal drive counter 10, and a deflection circuit 11. AFC consisting of 13 output AFC pulses, etc.
Loop circuit, 14 is a counter, 15 is an RS-flip-flop that triggers at the falling edge of a pulse,
16 is an inverter circuit, 17 is an OR gate circuit,
18 is a double-speed composite signal, A is a composite synchronization signal after separation, VD is a vertical synchronization signal, and E is a masked horizontal synchronization signal.
Claims (1)
、同期分離回路出力等のコンポジツト同期信号と
垂直同期信号とをそれぞれカウンタのクロツク入
力とクリア入力とに接続し、同カウンタのキヤリ
ー出力パルスと前記垂直同期信号を入力とするイ
ンバータ回路出力信号とを、それぞれパルス信号
の立ち下がりでトリガするＲＳ−フリツプフロツ
プ回路のセツト入力とリセツト入力とに接続し、
同ＲＳ−フリツプフロツプ回路出力と前記コンポ
ジツト同期信号とをオアゲート回路に接続し、同
ＲＳ−フリツプフロツプ回路出力信号のＨレベル
期間同オアゲート回路出力の水平同期信号等をマ
スキングしてなるテレビ受像機。 In a double speed conversion processing circuit such as a clear vision, a composite synchronization signal such as the output of a synchronization separation circuit and a vertical synchronization signal are connected to the clock input and clear input of a counter, respectively, and the carry output pulse of the counter and the vertical synchronization signal are input. and an inverter circuit output signal to a set input and a reset input of an RS-flip-flop circuit triggered by the falling edge of a pulse signal, respectively,
A television receiver comprising an RS-flip-flop circuit output and the composite synchronization signal connected to an OR gate circuit, and a horizontal synchronization signal output from the OR gate circuit being masked during an H level period of the RS-flip-flop circuit output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8884990U JPH0446492U (en) | 1990-08-24 | 1990-08-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8884990U JPH0446492U (en) | 1990-08-24 | 1990-08-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0446492U true JPH0446492U (en) | 1992-04-20 |
Family
ID=31822421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8884990U Pending JPH0446492U (en) | 1990-08-24 | 1990-08-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0446492U (en) |
-
1990
- 1990-08-24 JP JP8884990U patent/JPH0446492U/ja active Pending
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