JPH0451144U - - Google Patents

Info

Publication number
JPH0451144U
JPH0451144U JP1990091617U JP9161790U JPH0451144U JP H0451144 U JPH0451144 U JP H0451144U JP 1990091617 U JP1990091617 U JP 1990091617U JP 9161790 U JP9161790 U JP 9161790U JP H0451144 U JPH0451144 U JP H0451144U
Authority
JP
Japan
Prior art keywords
resin
substrate
semiconductor device
groove
sealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990091617U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990091617U priority Critical patent/JPH0451144U/ja
Publication of JPH0451144U publication Critical patent/JPH0451144U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Landscapes

  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第１図は本考案の実施例を示す樹脂封止型半導
体装置の断面図、第２図はその樹脂封止型半導体
装置の部分断面図、第３図はその樹脂封止型半導
体装置の部分平面図、第４図は従来の樹脂封止型
半導体装置の断面図、第５図は従来の樹脂封止型
半導体装置の平面図、第６図は従来の樹脂封止型
半導体装置の製造工程フローチヤートである。 １１……基板、１２ａ，１２ｂ……封止樹脂充
填用の溝、１２ｃ……テーパ、１３……配線。

Claims (1)

  1. 【実用新案登録請求の範囲】 基板へ半導体素子を実装し、該半導体素子を基
    板間を樹脂封止してなる半導体装置において、 前記基板上のコーナ部を含む配線パターン間に
    前記基板の中心から外方に向かつて深くなるテー
    パを有する溝を形成し、樹脂を充填することを特
    徴とする樹脂封止型半導体装置。
JP1990091617U 1990-09-03 1990-09-03 Pending JPH0451144U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990091617U JPH0451144U (ja) 1990-09-03 1990-09-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990091617U JPH0451144U (ja) 1990-09-03 1990-09-03

Publications (1)

Publication Number Publication Date
JPH0451144U true JPH0451144U (ja) 1992-04-30

Family

ID=31827421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990091617U Pending JPH0451144U (ja) 1990-09-03 1990-09-03

Country Status (1)

Country Link
JP (1) JPH0451144U (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1126645A (ja) * 1997-07-03 1999-01-29 Mitsubishi Electric Corp 半導体集積回路装置とその製造方法
WO2003003445A1 (fr) * 2001-06-29 2003-01-09 Fujitsu Limited Feuille de remplissage sous-jacent, procede de remplissage sous-jacent d'une puce semi-conductrice, et procede de montage d'une puce semi-conductrice
WO2008078746A1 (ja) * 2006-12-26 2008-07-03 Panasonic Corporation 半導体素子の実装構造体及び半導体素子の実装方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1126645A (ja) * 1997-07-03 1999-01-29 Mitsubishi Electric Corp 半導体集積回路装置とその製造方法
WO2003003445A1 (fr) * 2001-06-29 2003-01-09 Fujitsu Limited Feuille de remplissage sous-jacent, procede de remplissage sous-jacent d'une puce semi-conductrice, et procede de montage d'une puce semi-conductrice
JP4778667B2 (ja) * 2001-06-29 2011-09-21 富士通株式会社 アンダーフィル用シート材、半導体チップのアンダーフィル方法および半導体チップの実装方法
WO2008078746A1 (ja) * 2006-12-26 2008-07-03 Panasonic Corporation 半導体素子の実装構造体及び半導体素子の実装方法
JP5039058B2 (ja) * 2006-12-26 2012-10-03 パナソニック株式会社 半導体素子の実装構造体

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