JPH0451153U - - Google Patents

Info

Publication number
JPH0451153U
JPH0451153U JP1990092849U JP9284990U JPH0451153U JP H0451153 U JPH0451153 U JP H0451153U JP 1990092849 U JP1990092849 U JP 1990092849U JP 9284990 U JP9284990 U JP 9284990U JP H0451153 U JPH0451153 U JP H0451153U
Authority
JP
Japan
Prior art keywords
chips
chip
semiconductor device
same
packaged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990092849U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990092849U priority Critical patent/JPH0451153U/ja
Publication of JPH0451153U publication Critical patent/JPH0451153U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5445Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第1図はこの考案の一実施例による半導体装置
の断面図、第2図は第1図の上面図、第3図は従
来の半導体装置の断面図である。 図において、1,2は第1、第2のICチツプ
、3は金属ワイヤ、4は内部リード、5は外部リ
ード、6はモールドパツケージ、7は接続部分、
7a,7bは接続部、8はパツド、10はダイパ
ツドである。なお図中同一符号は同一又は相当部
分を示す。

Claims (1)

  1. 【実用新案登録請求の範囲】 所定の機能を有する第1のICチツプをフレー
    ム上にアセンブリし、 該第1のICチツプ上に、これと同一あるいは
    異なる機能を有する第2のICチツプを両チツプ
    間で相互に信号の入出力可能に搭載し、 上記両ICチツプ全体をパツケージングしてな
    ることを特徴とする半導体装置。
JP1990092849U 1990-09-03 1990-09-03 Pending JPH0451153U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990092849U JPH0451153U (ja) 1990-09-03 1990-09-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990092849U JPH0451153U (ja) 1990-09-03 1990-09-03

Publications (1)

Publication Number Publication Date
JPH0451153U true JPH0451153U (ja) 1992-04-30

Family

ID=31829620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990092849U Pending JPH0451153U (ja) 1990-09-03 1990-09-03

Country Status (1)

Country Link
JP (1) JPH0451153U (ja)

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