JPH0459175U - - Google Patents
Info
- Publication number
- JPH0459175U JPH0459175U JP1990101067U JP10106790U JPH0459175U JP H0459175 U JPH0459175 U JP H0459175U JP 1990101067 U JP1990101067 U JP 1990101067U JP 10106790 U JP10106790 U JP 10106790U JP H0459175 U JPH0459175 U JP H0459175U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- recognition means
- conductor pattern
- recognition
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
Description
第1図は本考案の実施例に係るプリント基板の
部分平面図、第2図は本考案の実施例に係るワイ
ヤボンデイングを説明するフローチヤート、第3
A図は視覚センサによる認識機能付のロボツトで
発生する認識点を示す図、第3B図は第3A図で
ICチツプ搭載のずれがある場合の認識点を示す
図、第4図は従来のプリント基板の部分平面図で
ある。 図において、1……ICチツプ、2……導体パ
ターン、3……チツプパツド、4……認識マーク
、5……ダイボンデイングパツド、6……ワイヤ
、7……プリント基板、A……ボンデイング指示
線、B……パターン形成等禁止部。
部分平面図、第2図は本考案の実施例に係るワイ
ヤボンデイングを説明するフローチヤート、第3
A図は視覚センサによる認識機能付のロボツトで
発生する認識点を示す図、第3B図は第3A図で
ICチツプ搭載のずれがある場合の認識点を示す
図、第4図は従来のプリント基板の部分平面図で
ある。 図において、1……ICチツプ、2……導体パ
ターン、3……チツプパツド、4……認識マーク
、5……ダイボンデイングパツド、6……ワイヤ
、7……プリント基板、A……ボンデイング指示
線、B……パターン形成等禁止部。
Claims (1)
- 【実用新案登録請求の範囲】 ICチツプ1と、該ICチツプ1に近接する導
体パターン2とを備え、前記ICチツプ1の搭載
位置を認識する第1の認識手段と該ICチツプ1
のチツプパツド3とワイヤで接続すべき導体パタ
ーン2の接続位置を認識するための第2の認識手
段とを有するプリント基板において、 前記第1および第2の認識手段を一体にして共
用し前記ICチツプ1をはさんで対向すると共に
該ICチツプ1に近接する前記導体パターン2の
端部で形成される領域の外側に配置される認識マ
ーク4を設けることを特徴とするプリント基板。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990101067U JPH0459175U (ja) | 1990-09-28 | 1990-09-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990101067U JPH0459175U (ja) | 1990-09-28 | 1990-09-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0459175U true JPH0459175U (ja) | 1992-05-21 |
Family
ID=31844210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990101067U Pending JPH0459175U (ja) | 1990-09-28 | 1990-09-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0459175U (ja) |
-
1990
- 1990-09-28 JP JP1990101067U patent/JPH0459175U/ja active Pending