JPH0480045U - - Google Patents

Info

Publication number
JPH0480045U
JPH0480045U JP12560590U JP12560590U JPH0480045U JP H0480045 U JPH0480045 U JP H0480045U JP 12560590 U JP12560590 U JP 12560590U JP 12560590 U JP12560590 U JP 12560590U JP H0480045 U JPH0480045 U JP H0480045U
Authority
JP
Japan
Prior art keywords
wiring layer
integrated circuit
semiconductor integrated
anything
intersects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12560590U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12560590U priority Critical patent/JPH0480045U/ja
Publication of JPH0480045U publication Critical patent/JPH0480045U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例である半導体集積
回路のパターンを示す平面図、第2図は第1図の
−線における断面図、第3図は従来の半導体
集積回路のパターンを示す平面図、第4図は第3
図の−線における断面図である。 図において、1は第1の配線層、2は第2の配
線層、3は針当て解析用の針先を示す。なお、図
中、同一符号は同一、または相当部分を示す。
Fig. 1 is a plan view showing a pattern of a semiconductor integrated circuit which is an embodiment of this invention, Fig. 2 is a sectional view taken along the - line in Fig. 1, and Fig. 3 is a plan view showing a pattern of a conventional semiconductor integrated circuit. Figure 4 is the third
It is a sectional view taken along the - line in the figure. In the figure, 1 is a first wiring layer, 2 is a second wiring layer, and 3 is a needle tip for needle point analysis. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第1の配線層下にどこにも接続されず、前記第
1の配線層と交差する第2の配線層を設け、前記
第1の配線層に段差を設けたことを特徴とする半
導体集積回路。
A semiconductor integrated circuit characterized in that a second wiring layer is provided below the first wiring layer and is not connected to anything and intersects with the first wiring layer, and a step is provided in the first wiring layer.
JP12560590U 1990-11-27 1990-11-27 Pending JPH0480045U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12560590U JPH0480045U (en) 1990-11-27 1990-11-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12560590U JPH0480045U (en) 1990-11-27 1990-11-27

Publications (1)

Publication Number Publication Date
JPH0480045U true JPH0480045U (en) 1992-07-13

Family

ID=31873197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12560590U Pending JPH0480045U (en) 1990-11-27 1990-11-27

Country Status (1)

Country Link
JP (1) JPH0480045U (en)

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