JPH09180445A5 - - Google Patents

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Publication number
JPH09180445A5
JPH09180445A5 JP1996320402A JP32040296A JPH09180445A5 JP H09180445 A5 JPH09180445 A5 JP H09180445A5 JP 1996320402 A JP1996320402 A JP 1996320402A JP 32040296 A JP32040296 A JP 32040296A JP H09180445 A5 JPH09180445 A5 JP H09180445A5
Authority
JP
Japan
Prior art keywords
time delay
programmable time
delay device
terminal
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP1996320402A
Other languages
English (en)
Other versions
JPH09180445A (ja
Filing date
Publication date
Application filed filed Critical
Publication of JPH09180445A publication Critical patent/JPH09180445A/ja
Publication of JPH09180445A5 publication Critical patent/JPH09180445A5/ja
Withdrawn legal-status Critical Current

Links

Claims (4)

  1. 制御信号によって決定される時間遅延を有する、プログラム可能時間遅延装置であって、
    反転増幅器と、
    前記反転増幅器の入力端子とアース電位との間に接続されたコンデンサと、
    前記入力端子と前記アース電位との間に接続され、かつそのゲート端子が装置入力端子に接続された、放電トランジスタと、
    複数個の抵抗器と、
    複数個の充電トランジスタであって、各々の充電トランジスタが抵抗器と直列に接続され、かつ前記充電トランジスタの各々と前記抵抗器との対が前記反転増幅器の入力端子と電源電圧との間に接続される、前記複数個の充電トランジスタと、
    複数個のゲート装置であって、前記ゲート装置の各々が前記装置入力端子と充電トランジスタのゲート端子との間に接続され、かつ前記ゲート装置の各々が前記制御信号の１つに応答して充電トランジスタのゲート端子に前記入力信号を加える、前記複数個のゲート装置と、
    を含む、前記プログラム可能時間遅延装置。
  2. 請求項１に記載のプログラム可能時間遅延装置において、前記ゲート装置がＰ／Ｎゲート装置であり、かつ前記ゲート装置の制御端子が前記制御信号とそれに加えられる前記制御信号の補数信号とを有する、前記プログラム可能時間遅延装置。
  3. 請求項１に記載のプログラム可能時間遅延装置において、
    前記プログラム可能時間遅延装置の出力端子に接続されたカウンタ装置と、
    前記プログラム可能時間遅延装置の前記出力端子と前記プログラム可能時間遅延装置の前記入力端子とに接続された反転増幅器と、
    をさらに含む、前記プログラム可能時間遅延装置。
  4. 半導体メモリ技術で実施することができ、かつその時間遅延が複数個の制御信号に応答して決定されるプログラム可能時間遅延装置であって、
    直列方式で接続された複数個の時間遅延部品を含み、かつ前記部品の各々が、
    時間遅延回路と、
    制御信号の第１状態に応答して前記時間遅延回路の入力端子を入力信号に接続し、前記制御信号の第２状態が前記入力信号に前記時間遅延回路をバイパスさせる、ゲート装置と、
    前記プログラム可能時間遅延装置の出力端子に接続されるカウンタ装置と、
    前記プログラム可能時間遅延装置の前記出力端子と前記プログラム可能時間遅延装置の入力端子とに接続された反転増幅器と、
    を含む、前記プログラム可能時間遅延装置。
JP8320402A 1995-11-29 1996-11-29 プログラム可能時間遅延装置 Withdrawn JPH09180445A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US007676 1993-01-22
US767695P 1995-11-29 1995-11-29

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007101792A Division JP4279888B2 (ja) 1995-11-29 2007-04-09 プログラム可能時間遅延装置

Publications (2)

Publication Number Publication Date
JPH09180445A JPH09180445A (ja) 1997-07-11
JPH09180445A5 true JPH09180445A5 (ja) 2004-11-18

Family

ID=21727534

Family Applications (2)

Application Number Title Priority Date Filing Date
JP8320402A Withdrawn JPH09180445A (ja) 1995-11-29 1996-11-29 プログラム可能時間遅延装置
JP2007101792A Expired - Lifetime JP4279888B2 (ja) 1995-11-29 2007-04-09 プログラム可能時間遅延装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2007101792A Expired - Lifetime JP4279888B2 (ja) 1995-11-29 2007-04-09 プログラム可能時間遅延装置

Country Status (5)

Country Link
US (2) US5841707A (ja)
EP (1) EP0777232B1 (ja)
JP (2) JPH09180445A (ja)
KR (1) KR970029840A (ja)
DE (1) DE69626752T2 (ja)

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US5953263A (en) * 1997-02-10 1999-09-14 Rambus Inc. Synchronous memory device having a programmable register and method of controlling same
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US6173432B1 (en) 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
KR100261215B1 (ko) * 1997-07-29 2000-07-01 윤종용 클럭 버퍼 및 이를 포함하는 메모리 로직 복합 반도체장치
US6101197A (en) 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
JPH11154398A (ja) * 1997-11-20 1999-06-08 Oki Electric Ind Co Ltd 半導体記憶装置
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US5923613A (en) * 1998-03-18 1999-07-13 Etron Technology, Inc. Latched type clock synchronizer with additional 180°-phase shift clock
US6052746A (en) * 1998-04-14 2000-04-18 Motorola, Inc. Integrated circuit having programmable pull device configured to enable/disable first function in favor of second function according to predetermined scheme before/after reset
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US6111812A (en) * 1999-07-23 2000-08-29 Micron Technology, Inc. Method and apparatus for adjusting control signal timing in a memory device
KR100355229B1 (ko) * 2000-01-28 2002-10-11 삼성전자 주식회사 카스 명령의 동작 지연 기능을 구비한 반도체 메모리 장치및 이에 적용되는 버퍼와 신호전송 회로
JP3647364B2 (ja) * 2000-07-21 2005-05-11 Ｎｅｃエレクトロニクス株式会社 クロック制御方法及び回路
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
KR100446291B1 (ko) * 2001-11-07 2004-09-01 삼성전자주식회사 카스 레이턴시를 이용하여 락킹 레졸루션 조절이 가능한지연동기 루프 회로
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US7068564B2 (en) * 2003-06-29 2006-06-27 International Business Machines Corporation Timer lockout circuit for synchronous applications
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