JPH10503328A - 電子装置の製造方法 - Google Patents
電子装置の製造方法Info
- Publication number
- JPH10503328A JPH10503328A JP8533910A JP53391096A JPH10503328A JP H10503328 A JPH10503328 A JP H10503328A JP 8533910 A JP8533910 A JP 8533910A JP 53391096 A JP53391096 A JP 53391096A JP H10503328 A JPH10503328 A JP H10503328A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wafer
- semiconductor wafer
- contact window
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
- H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/928—Front and rear surface processing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Die Bonding (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.絶縁層上に配置された半導体材料層が設けられた半導体ウエファの第1側部 に、半導体素子および導体トラックを有する層構体を形成し、その後半導体ウエ ファを前記第1側部で支持ウエファに膠層により固着し、前記支持ウエファには 金属化層を設け、その後半導体ウエファの他の第2側部から前記絶縁層が露出さ れるまで材料除去を行い、且つ、前記絶縁層には接点窓を設け、前記層構体と前 記膠層の前記接点窓の区域とに開口を形成し、これら開口を前記支持ウエファの 前記金属化層まで延在させ、前記接点窓および斯くして形成された開口には導電 性素子を設けるようにして電子装置を製造に当たり、前記半導体ウエファを前記 支持ウエファに固着する前に半導体ウエファの第1側部から前記絶縁層に接点窓 を設け、次いでこの接点窓に前記絶縁層に対し選択的に除去し得る材料を充填し 、次いで半導体ウエファを支持ウエファに固着した後、且つ絶縁層を露出した後 半導体ウエファの第2側部から接点窓をあけるようにしたことを特徴とする電子 装置の製造方法。 2.前記層構体と前記半導体ウエファの第2側部から前記膠層とに開口をエッチ ングにより形成し、接点窓を有する絶縁層をマスクとして用い、半導体ウエファ が支持ウエファに固着された後に絶縁層を露出し、且つ接点窓をあけるようにし たことを特徴とする請求項1に記載の電子装置の製造方法。 3.前記半導体ウエファを前記支持ウエファに固着する前に半導体ウエファの第 1側部から前記絶縁層に接点窓を設け、次いでこの接点窓に層構体に属する層の うちのひとつをも接点窓内に堆積するような材料を充填することを特徴とする請 求項1または2に記載の電子装置の製造方法。 4.前記半導体ウエファを前記支持ウエファに固着する前に半導体ウエファの第 1側部から層構体をも設け、次いでこの層構体に前記接点窓にも充填される材料 を充填するようにしたことを特徴とする請求項1または2に記載の電子装置の製 造方法。 5.前記層構体の開口および前記接点窓には絶縁層半導体ウエファを前記支持ウ エファに固着する膠を充填することを特徴とする請求項4に記載の電子装置の 製造方法。 6.前記接点窓および前記層構体の開口には導電性素子を電気化学的に設けるよ うにしたことを特徴とする請求項1〜5の何れかの項に記載の電子装置の製造方 法。 7.前記層構体の開口は前記半導体ウエファの第1側部の導電性トラックを具え る層構体に設けるようにしたことを特徴とする請求項1〜6の何れかの項に記載 の電子装置の製造方法。 8.前記支持ウエファの前記半導体ウエファとは反対側の金属化層を設けるよう にしたことを特徴とする請求項1〜7の何れかの項に記載の電子装置の製造方法 。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| NL95201201.1 | 1995-05-10 | ||
| EP95201201 | 1995-05-10 | ||
| PCT/IB1996/000350 WO1996036072A2 (en) | 1995-05-10 | 1996-04-18 | Method of manufacturing a device, by which method a substrate with semiconductor element and conductor tracks is glued to a support body with metallization |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10503328A true JPH10503328A (ja) | 1998-03-24 |
| JP4060882B2 JP4060882B2 (ja) | 2008-03-12 |
Family
ID=8220279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53391096A Expired - Lifetime JP4060882B2 (ja) | 1995-05-10 | 1996-04-18 | 電子装置の製造方法 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5770487A (ja) |
| EP (1) | EP0770267B1 (ja) |
| JP (1) | JP4060882B2 (ja) |
| DE (1) | DE69622339T2 (ja) |
| TW (1) | TW297917B (ja) |
| WO (1) | WO1996036072A2 (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003503854A (ja) * | 1999-06-29 | 2003-01-28 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 半導体デバイス |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09509792A (ja) * | 1994-12-23 | 1997-09-30 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | 支持ウェーハ上に接着した半導体物質の層中に半導体素子が形成した半導体装置の製造方法 |
| US6027958A (en) * | 1996-07-11 | 2000-02-22 | Kopin Corporation | Transferred flexible integrated circuit |
| JP3116085B2 (ja) * | 1997-09-16 | 2000-12-11 | 東京農工大学長 | 半導体素子形成法 |
| JP3809733B2 (ja) * | 1998-02-25 | 2006-08-16 | セイコーエプソン株式会社 | 薄膜トランジスタの剥離方法 |
| US6355950B1 (en) * | 1998-09-23 | 2002-03-12 | Intel Corporation | Substrate interconnect for power distribution on integrated circuits |
| US6882045B2 (en) * | 1999-10-28 | 2005-04-19 | Thomas J. Massingill | Multi-chip module and method for forming and method for deplating defective capacitors |
| JP2001267578A (ja) * | 2000-03-17 | 2001-09-28 | Sony Corp | 薄膜半導体装置及びその製造方法 |
| US6906847B2 (en) * | 2000-12-07 | 2005-06-14 | Reflectivity, Inc | Spatial light modulators with light blocking/absorbing areas |
| US7056810B2 (en) | 2002-12-18 | 2006-06-06 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor apparatus, and semiconductor apparatus and electric appliance |
| US9012232B2 (en) * | 2005-07-15 | 2015-04-21 | Nipro Diagnostics, Inc. | Diagnostic strip coding system and related methods of use |
| GB2522565B (en) | 2011-06-27 | 2016-02-03 | Pragmatic Printing Ltd | Transistor and its method of manufacture |
| GB2492532B (en) * | 2011-06-27 | 2015-06-03 | Pragmatic Printing Ltd | Transistor and its method of manufacture |
| DE102011116409B3 (de) * | 2011-10-19 | 2013-03-07 | Austriamicrosystems Ag | Verfahren zur Herstellung dünner Halbleiterbauelemente |
| US20200249588A1 (en) * | 2019-02-01 | 2020-08-06 | Micro Engineering, Inc. | Adhesive residue removal apparatus and adhesive residue removal method |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3936930A (en) * | 1972-07-10 | 1976-02-10 | Rca Corporation | Method of making electrical connections for liquid crystal cells |
| JP2617798B2 (ja) * | 1989-09-22 | 1997-06-04 | 三菱電機株式会社 | 積層型半導体装置およびその製造方法 |
| US5256562A (en) * | 1990-12-31 | 1993-10-26 | Kopin Corporation | Method for manufacturing a semiconductor device using a circuit transfer film |
| JPH04320216A (ja) * | 1991-04-19 | 1992-11-11 | Nec Corp | 液晶表示パネルおよびその製造方法 |
| US5317433A (en) * | 1991-12-02 | 1994-05-31 | Canon Kabushiki Kaisha | Image display device with a transistor on one side of insulating layer and liquid crystal on the other side |
| JP2821830B2 (ja) * | 1992-05-14 | 1998-11-05 | セイコーインスツルメンツ株式会社 | 半導体薄膜素子その応用装置および半導体薄膜素子の製造方法 |
| US5591678A (en) * | 1993-01-19 | 1997-01-07 | He Holdings, Inc. | Process of manufacturing a microelectric device using a removable support substrate and etch-stop |
| US5537234A (en) * | 1993-01-19 | 1996-07-16 | Hughes Aircraft Company | Relective liquid crystal display including driver devices integrally formed in monocrystalline semiconductor layer and method of fabricating the display |
| US5479048A (en) * | 1994-02-04 | 1995-12-26 | Analog Devices, Inc. | Integrated circuit chip supported by a handle wafer and provided with means to maintain the handle wafer potential at a desired level |
| US5627106A (en) * | 1994-05-06 | 1997-05-06 | United Microelectronics Corporation | Trench method for three dimensional chip connecting during IC fabrication |
| BE1008384A3 (nl) * | 1994-05-24 | 1996-04-02 | Koninkl Philips Electronics Nv | Werkwijze voor het vervaardigen van halfgeleiderinrichtingen met halfgeleiderelementen gevormd in een op een dragerplak aangebrachte laag halfgeleidermateriaal. |
-
1996
- 1996-04-18 EP EP96908307A patent/EP0770267B1/en not_active Expired - Lifetime
- 1996-04-18 DE DE69622339T patent/DE69622339T2/de not_active Expired - Lifetime
- 1996-04-18 JP JP53391096A patent/JP4060882B2/ja not_active Expired - Lifetime
- 1996-04-18 WO PCT/IB1996/000350 patent/WO1996036072A2/en not_active Ceased
- 1996-04-24 TW TW085104876A patent/TW297917B/zh not_active IP Right Cessation
- 1996-04-29 US US08/641,058 patent/US5770487A/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003503854A (ja) * | 1999-06-29 | 2003-01-28 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 半導体デバイス |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1996036072A2 (en) | 1996-11-14 |
| TW297917B (ja) | 1997-02-11 |
| US5770487A (en) | 1998-06-23 |
| DE69622339D1 (de) | 2002-08-22 |
| WO1996036072A3 (en) | 1997-01-16 |
| DE69622339T2 (de) | 2003-03-06 |
| EP0770267A2 (en) | 1997-05-02 |
| JP4060882B2 (ja) | 2008-03-12 |
| EP0770267B1 (en) | 2002-07-17 |
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