JPH09509792A - 支持ウェーハ上に接着した半導体物質の層中に半導体素子が形成した半導体装置の製造方法 - Google Patents
支持ウェーハ上に接着した半導体物質の層中に半導体素子が形成した半導体装置の製造方法Info
- Publication number
- JPH09509792A JPH09509792A JP8520325A JP52032596A JPH09509792A JP H09509792 A JPH09509792 A JP H09509792A JP 8520325 A JP8520325 A JP 8520325A JP 52032596 A JP52032596 A JP 52032596A JP H09509792 A JPH09509792 A JP H09509792A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- wafer
- insulating
- protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7432—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07231—Techniques
- H10W72/07236—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
- H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/928—Front and rear surface processing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/958—Passivation layer
Landscapes
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.半導体装置を製造するにあたり、この方法が、第1の側に、絶縁層上に位置 する半導体物質の最上層を備えた半導体ウェーハで開始し、その後半導体素子お よび導電性トラックをこの半導体ウェーハの第1の側上に形成し、半導体ウェー ハのこの第1の側に支持ウェーハを接着し、物質を、半導体ウェーハの他方の第 2の側から、絶縁層が露出するまで除去する方法であって、 方法を開始する半導体ウェーハの絶縁層が、絶縁層でありかつ保護層である ことを特徴とする半導体装置の製造方法。 2.絶縁保護層が、保護物質のサブ層および絶縁物質のサブ層を有することを特 徴とする請求の範囲1記載の方法。 3.保護層のサブ層を、絶縁物質のサブ層により、いずれかの側に接着すること を特徴とする請求の範囲2記載の方法。 4.保護層のサブ層を、酸化ケイ素のサブ層により、いずれかの側に接着するこ とを特徴とする請求の範囲3記載の方法。 5.保護層のサブ層を、窒化ケイ素の層またはリンガラスの層あるいは窒化ケイ 素の層とリンガラスの層とから成る二重層により形成することを特徴とする請求 の範囲4記載の方法。 6.方法を開始する半導体ウェーハをウェーハ接着により得、これにより、第1 のケイ素ウェーハの1つの側に、酸化ケイ素の層、保護物質の層および酸化ケイ 素の層を連続的に設け、これにより、第2のウェーハの1つの側に酸化ケイ素の 層を設け、その後、これら2つのウェーハを、層を設けるこれらの側で、互いに 接着することを特徴とする請求の範囲5記載の方法。 7.第1のケイ素ウェーハ上の保護物質の層を、窒化ケイ素の層またはリンガラ スの層あるいは窒化ケイ素の層とリンガラスの層とから成る二重層により形成す ることを特徴とする請求の範囲6記載の方法。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AT94203751.6 | 1994-12-23 | ||
| EP94203751 | 1994-12-23 | ||
| PCT/IB1995/001080 WO1996020497A1 (en) | 1994-12-23 | 1995-11-29 | Method of manufacturing semiconductor devices with semiconductor elements formed in a layer of semiconductor material glued on a support wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09509792A true JPH09509792A (ja) | 1997-09-30 |
Family
ID=8217491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8520325A Pending JPH09509792A (ja) | 1994-12-23 | 1995-11-29 | 支持ウェーハ上に接着した半導体物質の層中に半導体素子が形成した半導体装置の製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5780354A (ja) |
| EP (1) | EP0746875B1 (ja) |
| JP (1) | JPH09509792A (ja) |
| DE (1) | DE69525739T2 (ja) |
| WO (1) | WO1996020497A1 (ja) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2744285B1 (fr) * | 1996-01-25 | 1998-03-06 | Commissariat Energie Atomique | Procede de transfert d'une couche mince d'un substrat initial sur un substrat final |
| WO1997034317A1 (en) * | 1996-03-12 | 1997-09-18 | Philips Electronics N.V. | Method of manufacturing a hybrid integrated circuit |
| JP3565090B2 (ja) * | 1998-07-06 | 2004-09-15 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
| DE19918671B4 (de) * | 1999-04-23 | 2006-03-02 | Giesecke & Devrient Gmbh | Vertikal integrierbare Schaltung und Verfahren zu ihrer Herstellung |
| KR20010071544A (ko) | 1999-04-23 | 2001-07-28 | 롤페스 요하네스 게라투스 알베르투스 | 연성 페라이트 재료로 이루어진 보디를 포함하는 50㎒보다큰 동작 주파수를 갖는 반도체 장치 |
| TW455964B (en) * | 2000-07-18 | 2001-09-21 | Siliconware Precision Industries Co Ltd | Multi-chip module package structure with stacked chips |
| JP2003023141A (ja) * | 2001-07-09 | 2003-01-24 | Tokyo Electron Ltd | 半導体基板の製造方法および半導体基板 |
| JP2003291343A (ja) * | 2001-10-26 | 2003-10-14 | Seiko Epson Corp | 液体噴射ヘッド及びその製造方法並びに液体噴射装置 |
| FR2871291B1 (fr) * | 2004-06-02 | 2006-12-08 | Tracit Technologies | Procede de transfert de plaques |
| US7268012B2 (en) * | 2004-08-31 | 2007-09-11 | Micron Technology, Inc. | Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby |
| DE102007034306B3 (de) * | 2007-07-24 | 2009-04-02 | Austriamicrosystems Ag | Halbleitersubstrat mit Durchkontaktierung und Verfahren zur Herstellung eines Halbleitersubstrates mit Durchkontaktierung |
| JP2018081945A (ja) * | 2016-11-14 | 2018-05-24 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像素子および製造方法、並びに電子機器 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4468857A (en) * | 1983-06-27 | 1984-09-04 | Teletype Corporation | Method of manufacturing an integrated circuit device |
| US4870475A (en) * | 1985-11-01 | 1989-09-26 | Nec Corporation | Semiconductor device and method of manufacturing the same |
| JPS63308386A (ja) * | 1987-01-30 | 1988-12-15 | Sony Corp | 半導体装置とその製造方法 |
| US5065222A (en) * | 1987-11-11 | 1991-11-12 | Seiko Instruments Inc. | Semiconductor device having two-layered passivation film |
| JPH0344067A (ja) * | 1989-07-11 | 1991-02-25 | Nec Corp | 半導体基板の積層方法 |
| JP2617798B2 (ja) * | 1989-09-22 | 1997-06-04 | 三菱電機株式会社 | 積層型半導体装置およびその製造方法 |
| US5362667A (en) * | 1992-07-28 | 1994-11-08 | Harris Corporation | Bonded wafer processing |
| US5289031A (en) * | 1990-08-21 | 1994-02-22 | Kabushiki Kaisha Toshiba | Semiconductor device capable of blocking contaminants |
| US5376561A (en) * | 1990-12-31 | 1994-12-27 | Kopin Corporation | High density electronic circuit modules |
| JP2821830B2 (ja) * | 1992-05-14 | 1998-11-05 | セイコーインスツルメンツ株式会社 | 半導体薄膜素子その応用装置および半導体薄膜素子の製造方法 |
| US5403729A (en) * | 1992-05-27 | 1995-04-04 | Micro Technology Partners | Fabricating a semiconductor with an insulative coating |
| EP0646286B1 (en) * | 1992-06-17 | 2002-10-16 | Harris Corporation | Fabrication of semiconductor devices on SOI substrates |
| US5270221A (en) * | 1992-11-05 | 1993-12-14 | Hughes Aircraft Company | Method of fabricating high quantum efficiency solid state sensors |
| JP3158749B2 (ja) * | 1992-12-16 | 2001-04-23 | ヤマハ株式会社 | 半導体装置 |
| US5426072A (en) * | 1993-01-21 | 1995-06-20 | Hughes Aircraft Company | Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate |
| JPH06296023A (ja) * | 1993-02-10 | 1994-10-21 | Semiconductor Energy Lab Co Ltd | 薄膜状半導体装置およびその作製方法 |
| JP3265718B2 (ja) * | 1993-06-23 | 2002-03-18 | 株式会社日立製作所 | Si転写マスク、及び、Si転写マスクの製造方法 |
| EP0770267B1 (en) * | 1995-05-10 | 2002-07-17 | Koninklijke Philips Electronics N.V. | Method of manufacturing a device, by which method a substrate with semiconductor element and conductor tracks is glued to a support body with metallization |
-
1995
- 1995-11-29 JP JP8520325A patent/JPH09509792A/ja active Pending
- 1995-11-29 DE DE69525739T patent/DE69525739T2/de not_active Expired - Lifetime
- 1995-11-29 WO PCT/IB1995/001080 patent/WO1996020497A1/en not_active Ceased
- 1995-11-29 EP EP95936730A patent/EP0746875B1/en not_active Expired - Lifetime
- 1995-12-21 US US08/576,538 patent/US5780354A/en not_active Expired - Lifetime
-
1998
- 1998-05-18 US US09/080,784 patent/US6104081A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| DE69525739T2 (de) | 2002-10-02 |
| WO1996020497A1 (en) | 1996-07-04 |
| EP0746875A1 (en) | 1996-12-11 |
| US6104081A (en) | 2000-08-15 |
| US5780354A (en) | 1998-07-14 |
| EP0746875B1 (en) | 2002-03-06 |
| DE69525739D1 (de) | 2002-04-11 |
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