JPH118305A - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法

Info

Publication number
JPH118305A
JPH118305A JP9156724A JP15672497A JPH118305A JP H118305 A JPH118305 A JP H118305A JP 9156724 A JP9156724 A JP 9156724A JP 15672497 A JP15672497 A JP 15672497A JP H118305 A JPH118305 A JP H118305A
Authority
JP
Japan
Prior art keywords
opening
semiconductor device
conductive layer
film
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9156724A
Other languages
English (en)
Japanese (ja)
Other versions
JPH118305A5 (2
Inventor
Takahiro Kawasaki
孝博 河崎
Shigeru Harada
繁 原田
Hiroshi Tobimatsu
博 飛松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Engineering Corp
Mitsubishi Electric Corp
Original Assignee
Renesas Semiconductor Engineering Corp
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Engineering Corp, Mitsubishi Electric Corp filed Critical Renesas Semiconductor Engineering Corp
Priority to JP9156724A priority Critical patent/JPH118305A/ja
Priority to TW086115858A priority patent/TW356586B/zh
Priority to DE19750896A priority patent/DE19750896B4/de
Priority to US08/985,218 priority patent/US6046488A/en
Publication of JPH118305A publication Critical patent/JPH118305A/ja
Publication of JPH118305A5 publication Critical patent/JPH118305A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
    • H10W20/494—Fuses, i.e. interconnections changeable from conductive to non-conductive changeable by the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
JP9156724A 1997-06-13 1997-06-13 半導体装置およびその製造方法 Pending JPH118305A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP9156724A JPH118305A (ja) 1997-06-13 1997-06-13 半導体装置およびその製造方法
TW086115858A TW356586B (en) 1997-06-13 1997-10-27 Semiconductor device having conductive layer and manufacturing method thereof
DE19750896A DE19750896B4 (de) 1997-06-13 1997-11-17 Halbleitereinrichtung mit einer leitenden Schicht und ihr Herstellungsverfahren
US08/985,218 US6046488A (en) 1997-06-13 1997-12-04 Semiconductor device having conductive layer and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9156724A JPH118305A (ja) 1997-06-13 1997-06-13 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
JPH118305A true JPH118305A (ja) 1999-01-12
JPH118305A5 JPH118305A5 (2) 2004-07-08

Family

ID=15633954

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9156724A Pending JPH118305A (ja) 1997-06-13 1997-06-13 半導体装置およびその製造方法

Country Status (4)

Country Link
US (1) US6046488A (2)
JP (1) JPH118305A (2)
DE (1) DE19750896B4 (2)
TW (1) TW356586B (2)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7268068B2 (en) 2000-09-14 2007-09-11 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3049001B2 (ja) * 1998-02-12 2000-06-05 日本電気アイシーマイコンシステム株式会社 ヒューズ装置およびその製造方法
JP3239843B2 (ja) * 1998-05-11 2001-12-17 関西日本電気株式会社 半導体装置の製造方法
KR100351050B1 (ko) * 1999-11-26 2002-09-10 삼성전자 주식회사 반도체소자의 퓨즈부 형성방법
US7238620B1 (en) 2004-02-18 2007-07-03 National Semiconductor Corporation System and method for providing a uniform oxide layer over a laser trimmed fuse with a differential wet etch stop technique
JP4584657B2 (ja) * 2004-09-13 2010-11-24 Ｏｋｉセミコンダクタ株式会社 半導体装置
DE102006046790B4 (de) * 2006-10-02 2014-01-02 Infineon Technologies Ag Integriertes Bauelement und Verfahren zum Trennen einer elektrisch leitfähigen Verbindung

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5877246A (ja) * 1981-11-02 1983-05-10 Hitachi Ltd 多層配線構造の形成方法
US4853758A (en) * 1987-08-12 1989-08-01 American Telephone And Telegraph Company, At&T Bell Laboratories Laser-blown links
US5235205A (en) * 1991-04-23 1993-08-10 Harris Corporation Laser trimmed integrated circuit
US5374792A (en) * 1993-01-04 1994-12-20 General Electric Company Micromechanical moving structures including multiple contact switching system
US5365104A (en) * 1993-03-25 1994-11-15 Paradigm Technology, Inc. Oxynitride fuse protective/passivation film for integrated circuit having resistors
US5747868A (en) * 1995-06-26 1998-05-05 Alliance Semiconductor Corporation Laser fusible link structure for semiconductor devices
US5538924A (en) * 1995-09-05 1996-07-23 Vanguard International Semiconductor Co. Method of forming a moisture guard ring for integrated circuit applications
JPH09153552A (ja) * 1995-11-29 1997-06-10 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5652175A (en) * 1996-07-19 1997-07-29 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing a fuse structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7268068B2 (en) 2000-09-14 2007-09-11 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
DE19750896B4 (de) 2004-09-16
US6046488A (en) 2000-04-04
TW356586B (en) 1999-04-21
DE19750896A1 (de) 1998-12-17

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