JPS5541018A - Programmable counter - Google Patents

Programmable counter

Info

Publication number
JPS5541018A
JPS5541018A JP11382578A JP11382578A JPS5541018A JP S5541018 A JPS5541018 A JP S5541018A JP 11382578 A JP11382578 A JP 11382578A JP 11382578 A JP11382578 A JP 11382578A JP S5541018 A JPS5541018 A JP S5541018A
Authority
JP
Japan
Prior art keywords
gates
propagation delay
nand
terminal
cet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11382578A
Other languages
Japanese (ja)
Other versions
JPS6013612B2 (en
Inventor
Hiroyuki Kikuchi
Atsushi Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11382578A priority Critical patent/JPS6013612B2/en
Publication of JPS5541018A publication Critical patent/JPS5541018A/en
Publication of JPS6013612B2 publication Critical patent/JPS6013612B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses

Landscapes

  • Logic Circuits (AREA)

Abstract

PURPOSE:To realize the programmable counter of complementary MOS constitution small in the propagation delay time and less in the number of circuit elements, by constituting AND, OR and exclusive NOR gates with NAND and transmission gates. CONSTITUTION:When the LOAD terminal is high, the output of the NAND gate 22 is high. If either of CEP or CET terminal is low, FF33 is held at prestage. But, if the CEP and CET terminal are all high, FF33 is inverted and the count is advanced. The propagation delay from the operation of FF33 when the count is made until the D input is confirmed consists of the delays in the transmission gate 25 and NAND gates 31 and 32. Accordingly, the propagation delay can be made less. Further, the number of gates can remarkably be reduced.
JP11382578A 1978-09-16 1978-09-16 programmable counter Expired JPS6013612B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11382578A JPS6013612B2 (en) 1978-09-16 1978-09-16 programmable counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11382578A JPS6013612B2 (en) 1978-09-16 1978-09-16 programmable counter

Publications (2)

Publication Number Publication Date
JPS5541018A true JPS5541018A (en) 1980-03-22
JPS6013612B2 JPS6013612B2 (en) 1985-04-08

Family

ID=14621981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11382578A Expired JPS6013612B2 (en) 1978-09-16 1978-09-16 programmable counter

Country Status (1)

Country Link
JP (1) JPS6013612B2 (en)

Also Published As

Publication number Publication date
JPS6013612B2 (en) 1985-04-08

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