JPS5583265A - Semiconductor device and method of fabricating the same - Google Patents

Semiconductor device and method of fabricating the same

Info

Publication number
JPS5583265A
JPS5583265A JP15835478A JP15835478A JPS5583265A JP S5583265 A JPS5583265 A JP S5583265A JP 15835478 A JP15835478 A JP 15835478A JP 15835478 A JP15835478 A JP 15835478A JP S5583265 A JPS5583265 A JP S5583265A
Authority
JP
Japan
Prior art keywords
region
film
type element
element region
ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15835478A
Other languages
Japanese (ja)
Inventor
Kazunari Shirai
Takehide Shirato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15835478A priority Critical patent/JPS5583265A/en
Publication of JPS5583265A publication Critical patent/JPS5583265A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0163—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including enhancement-mode IGFETs and depletion-mode IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To provide an E/D mode MOSIC having a multilayer electrode constuction by isolating a silicon substrate by a thick field oxide film, providing a thin gate oxide film thereat as an enhancemenet type element region, and implanting ion to the adjacent region thereto to thereby form a depletion type element region. CONSTITUTION:A plurality of thick field oxide films 2 are formed on a p-type silicon substrate 1, films 3 becoming thin gate oxide films are coated therebetween, and ion is implanted into the substrate 1 under the film 3 to thereby form a p-type region 31 for controlling the threshold voltage of an enhancement type element. Then, the film 3 on the region 31 is selectively retained, a polycrystalline silicon gate electrode 4 is formed on the film 3, and a polycrystalline silicon wires 4' are formed on the film 2. Then, with the wires 4' as mask ion is implanted to thereby alter the portion under the region 31 into an n-channel layer 32 and the layer 32 of the other region interposed with the film 2 into a depletion type element region. Simultaneously, n-type source and drain regions 33 and 34 are formed in the enhancement type element region, and source and drain regions 35 and 36 are formed in the depletion type element region.
JP15835478A 1978-12-19 1978-12-19 Semiconductor device and method of fabricating the same Pending JPS5583265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15835478A JPS5583265A (en) 1978-12-19 1978-12-19 Semiconductor device and method of fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15835478A JPS5583265A (en) 1978-12-19 1978-12-19 Semiconductor device and method of fabricating the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP61304944A Division JPS6323348A (en) 1986-12-18 1986-12-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5583265A true JPS5583265A (en) 1980-06-23

Family

ID=15669817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15835478A Pending JPS5583265A (en) 1978-12-19 1978-12-19 Semiconductor device and method of fabricating the same

Country Status (1)

Country Link
JP (1) JPS5583265A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4627153A (en) * 1981-02-06 1986-12-09 Tokyo Shibaura Denki Kabushiki Kaisha Method of producing a semiconductor memory device
JPS6323348A (en) * 1986-12-18 1988-01-30 Fujitsu Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4627153A (en) * 1981-02-06 1986-12-09 Tokyo Shibaura Denki Kabushiki Kaisha Method of producing a semiconductor memory device
JPS6323348A (en) * 1986-12-18 1988-01-30 Fujitsu Ltd Manufacture of semiconductor device

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