JPS5673473A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPS5673473A
JPS5673473A JP15297080A JP15297080A JPS5673473A JP S5673473 A JPS5673473 A JP S5673473A JP 15297080 A JP15297080 A JP 15297080A JP 15297080 A JP15297080 A JP 15297080A JP S5673473 A JPS5673473 A JP S5673473A
Authority
JP
Japan
Prior art keywords
gate electrode
substrate
film
polycrystal
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15297080A
Other languages
English (en)
Inventor
Sen Fuu Hongu
Eru Mooru Jiyon
Manorii Jieriana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Japan Inc
Original Assignee
Yokogawa Hewlett Packard Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hewlett Packard Ltd filed Critical Yokogawa Hewlett Packard Ltd
Publication of JPS5673473A publication Critical patent/JPS5673473A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0113Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/02Contacts, special
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/051Etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/147Silicides

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP15297080A 1979-11-06 1980-10-30 Manufacture of semiconductor element Pending JPS5673473A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/091,845 US4305200A (en) 1979-11-06 1979-11-06 Method of forming self-registering source, drain, and gate contacts for FET transistor structures

Publications (1)

Publication Number Publication Date
JPS5673473A true JPS5673473A (en) 1981-06-18

Family

ID=22229926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15297080A Pending JPS5673473A (en) 1979-11-06 1980-10-30 Manufacture of semiconductor element

Country Status (4)

Country Link
US (1) US4305200A (ja)
JP (1) JPS5673473A (ja)
DE (1) DE3031708A1 (ja)
GB (1) GB2062959A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216447A (ja) * 1985-03-22 1986-09-26 Fujitsu Ltd 半導体装置の製造方法

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5696850A (en) * 1979-12-30 1981-08-05 Fujitsu Ltd Semiconductor device and manufacture thereof
US4476478A (en) * 1980-04-24 1984-10-09 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor read only memory and method of making the same
US4883543A (en) * 1980-06-05 1989-11-28 Texas Instruments Incroporated Shielding for implant in manufacture of dynamic memory
JPS5737888A (en) * 1980-08-19 1982-03-02 Mitsubishi Electric Corp Photo detector
US4380866A (en) * 1981-05-04 1983-04-26 Motorola, Inc. Method of programming ROM by offset masking of selected gates
US4445266A (en) * 1981-08-07 1984-05-01 Mostek Corporation MOSFET Fabrication process for reducing overlap capacitance and lowering interconnect impedance
US4518981A (en) * 1981-11-12 1985-05-21 Advanced Micro Devices, Inc. Merged platinum silicide fuse and Schottky diode and method of manufacture thereof
DE3211761A1 (de) * 1982-03-30 1983-10-06 Siemens Ag Verfahren zum herstellen von integrierten mos-feldeffekttransistorschaltungen in siliziumgate-technologie mit silizid beschichteten diffusionsgebieten als niederohmige leiterbahnen
JPS58175846A (ja) * 1982-04-08 1983-10-15 Toshiba Corp 半導体装置の製造方法
JPH0618213B2 (ja) * 1982-06-25 1994-03-09 松下電子工業株式会社 半導体装置の製造方法
DE3304588A1 (de) * 1983-02-10 1984-08-16 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von mos-transistoren mit flachen source/drain-gebieten, kurzen kanallaengen und einer selbstjustierten, aus einem metallsilizid bestehenden kontaktierungsebene
GB2139418A (en) * 1983-05-05 1984-11-07 Standard Telephones Cables Ltd Semiconductor devices and conductors therefor
FR2555365B1 (fr) * 1983-11-22 1986-08-29 Efcis Procede de fabrication de circuit integre avec connexions de siliciure de tantale et circuit integre realise selon ce procede
US4716131A (en) * 1983-11-28 1987-12-29 Nec Corporation Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film
US4519126A (en) * 1983-12-12 1985-05-28 Rca Corporation Method of fabricating high speed CMOS devices
US4563805A (en) * 1984-03-08 1986-01-14 Standard Telephones And Cables, Plc Manufacture of MOSFET with metal silicide contact
FR2562327B1 (fr) * 1984-03-30 1986-06-20 Commissariat Energie Atomique Procede pour interconnecter les zones actives et/ou les grilles des circuits integres cmos
US4609568A (en) * 1984-07-27 1986-09-02 Fairchild Camera & Instrument Corporation Self-aligned metal silicide process for integrated circuits having self-aligned polycrystalline silicon electrodes
US4706870A (en) * 1984-12-18 1987-11-17 Motorola Inc. Controlled chemical reduction of surface film
JPS61150369A (ja) * 1984-12-25 1986-07-09 Toshiba Corp 読み出し専用半導体記憶装置およびその製造方法
FR2576710B1 (fr) * 1985-01-25 1988-03-04 Thomson Csf Procede d'obtention d'une diode dont la prise de contact est auto-alignee a une grille
US5072275A (en) * 1986-02-28 1991-12-10 Fairchild Semiconductor Corporation Small contactless RAM cell
US5340762A (en) * 1985-04-01 1994-08-23 Fairchild Semiconductor Corporation Method of making small contactless RAM cell
US5100824A (en) * 1985-04-01 1992-03-31 National Semiconductor Corporation Method of making small contactless RAM cell
JPS6230351A (ja) * 1985-04-25 1987-02-09 Nec Corp 半導体装置の製造方法
DE3683679D1 (de) * 1985-04-26 1992-03-12 Fujitsu Ltd Verfahren zur herstellung einer kontaktanordnung fuer eine halbleiteranordnung.
US4804636A (en) * 1985-05-01 1989-02-14 Texas Instruments Incorporated Process for making integrated circuits having titanium nitride triple interconnect
US4821085A (en) * 1985-05-01 1989-04-11 Texas Instruments Incorporated VLSI local interconnect structure
US5063168A (en) * 1986-07-02 1991-11-05 National Semiconductor Corporation Process for making bipolar transistor with polysilicon stringer base contact
US4974046A (en) * 1986-07-02 1990-11-27 National Seimconductor Corporation Bipolar transistor with polysilicon stringer base contact
JPS63198323A (ja) * 1987-02-13 1988-08-17 Mitsubishi Electric Corp 半導体装置およびその製造方法
US4994402A (en) * 1987-06-26 1991-02-19 Hewlett-Packard Company Method of fabricating a coplanar, self-aligned contact structure in a semiconductor device
US5153701A (en) * 1987-12-28 1992-10-06 At&T Bell Laboratories Semiconductor device with low defect density oxide
US4910168A (en) * 1988-05-06 1990-03-20 Mos Electronics Corporation Method to reduce silicon area for via formation
JP2904533B2 (ja) * 1989-03-09 1999-06-14 株式会社東芝 半導体装置の製造方法
KR920010062B1 (ko) * 1989-04-03 1992-11-13 현대전자산업 주식회사 반도체 장치의 실리사이드 형성방법
US5679968A (en) * 1990-01-31 1997-10-21 Texas Instruments Incorporated Transistor having reduced hot carrier implantation
JPH0637317A (ja) * 1990-04-11 1994-02-10 General Motors Corp <Gm> 薄膜トランジスタおよびその製造方法
US5272099A (en) * 1992-11-27 1993-12-21 Etron Technology Inc. Fabrication of transistor contacts
US6730549B1 (en) 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
JPH0766424A (ja) 1993-08-20 1995-03-10 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JPH07106570A (ja) * 1993-10-05 1995-04-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6706572B1 (en) 1994-08-31 2004-03-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a thin film transistor using a high pressure oxidation step
US6127276A (en) * 1998-06-02 2000-10-03 United Microelectronics Corp Method of formation for a via opening
US6235630B1 (en) 1998-08-19 2001-05-22 Micron Technology, Inc. Silicide pattern structures and methods of fabricating the same
US6090673A (en) * 1998-10-20 2000-07-18 International Business Machines Corporation Device contact structure and method for fabricating same
US6429124B1 (en) * 1999-04-14 2002-08-06 Micron Technology, Inc. Local interconnect structures for integrated circuits and methods for making the same
US7906440B2 (en) * 2005-02-01 2011-03-15 Tokyo Electron Limited Semiconductor device manufacturing method and plasma oxidation method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4931286A (ja) * 1972-02-26 1974-03-20
JPS51433A (en) * 1974-06-21 1976-01-06 Ueyama Jitsugyo Kk Gorufurenshujono boorukaishusochi
JPS5296873A (en) * 1976-06-26 1977-08-15 Tdk Corp Mos type field effect transistor and its manufacture

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7510903A (nl) * 1975-09-17 1977-03-21 Philips Nv Werkwijze voor het vervaardigen van een halfgelei- derinrichting, en inrichting vervaardigd volgens de werkwijze.
JPS6041470B2 (ja) * 1976-06-15 1985-09-17 松下電器産業株式会社 半導体装置の製造方法
US4136434A (en) * 1977-06-10 1979-01-30 Bell Telephone Laboratories, Incorporated Fabrication of small contact openings in large-scale-integrated devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4931286A (ja) * 1972-02-26 1974-03-20
JPS51433A (en) * 1974-06-21 1976-01-06 Ueyama Jitsugyo Kk Gorufurenshujono boorukaishusochi
JPS5296873A (en) * 1976-06-26 1977-08-15 Tdk Corp Mos type field effect transistor and its manufacture

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61216447A (ja) * 1985-03-22 1986-09-26 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
GB2062959A (en) 1981-05-28
DE3031708A1 (de) 1981-05-14
US4305200A (en) 1981-12-15

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