JPS57211251A - Manufacture of semiconductor integrated circuit - Google Patents

Manufacture of semiconductor integrated circuit

Info

Publication number
JPS57211251A
JPS57211251A JP56096908A JP9690881A JPS57211251A JP S57211251 A JPS57211251 A JP S57211251A JP 56096908 A JP56096908 A JP 56096908A JP 9690881 A JP9690881 A JP 9690881A JP S57211251 A JPS57211251 A JP S57211251A
Authority
JP
Japan
Prior art keywords
layer
insulating film
polycrystalline
si3n4
covered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56096908A
Other languages
English (en)
Japanese (ja)
Other versions
JPS639748B2 (fr
Inventor
Yoshitaka Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56096908A priority Critical patent/JPS57211251A/ja
Priority to US06/389,939 priority patent/US4625391A/en
Priority to DE8282105505T priority patent/DE3277345D1/de
Priority to EP82105505A priority patent/EP0070402B1/fr
Publication of JPS57211251A publication Critical patent/JPS57211251A/ja
Publication of JPS639748B2 publication Critical patent/JPS639748B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/412—Deposition of metallic or metal-silicide materials
    • H10P14/414—Deposition of metallic or metal-silicide materials of metal-silicide materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/30—Diffusion for doping of conductive or resistive layers
    • H10P32/302—Doping polycrystalline silicon or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/065—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by making at least a portion of the conductive part non-conductive, e.g. by oxidation

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)
JP56096908A 1981-06-23 1981-06-23 Manufacture of semiconductor integrated circuit Granted JPS57211251A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP56096908A JPS57211251A (en) 1981-06-23 1981-06-23 Manufacture of semiconductor integrated circuit
US06/389,939 US4625391A (en) 1981-06-23 1982-06-18 Semiconductor device and method for manufacturing the same
DE8282105505T DE3277345D1 (en) 1981-06-23 1982-06-23 Method of forming electrically conductive patterns on a semiconductor device, and a semiconductor device manufactured by the method
EP82105505A EP0070402B1 (fr) 1981-06-23 1982-06-23 Procédé pour former des configurations électroconductrices sur un dispositif semiconducteur, et un dispositif semiconducteur fabriqué par le procédé

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56096908A JPS57211251A (en) 1981-06-23 1981-06-23 Manufacture of semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS57211251A true JPS57211251A (en) 1982-12-25
JPS639748B2 JPS639748B2 (fr) 1988-03-01

Family

ID=14177454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56096908A Granted JPS57211251A (en) 1981-06-23 1981-06-23 Manufacture of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS57211251A (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61274359A (ja) * 1985-04-01 1986-12-04 フエアチヤイルド　セミコンダクタ　コ−ポレ−シヨン 小型コンタクト無しｒａｍセル
JPS6278852A (ja) * 1985-09-30 1987-04-11 Nec Corp 半導体装置の製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54127688A (en) * 1978-03-28 1979-10-03 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
JPS54154966A (en) * 1978-05-29 1979-12-06 Nippon Telegr & Teleph Corp <Ntt> Semiconductor electron device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54127688A (en) * 1978-03-28 1979-10-03 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
JPS54154966A (en) * 1978-05-29 1979-12-06 Nippon Telegr & Teleph Corp <Ntt> Semiconductor electron device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61274359A (ja) * 1985-04-01 1986-12-04 フエアチヤイルド　セミコンダクタ　コ−ポレ−シヨン 小型コンタクト無しｒａｍセル
JPS6278852A (ja) * 1985-09-30 1987-04-11 Nec Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
JPS639748B2 (fr) 1988-03-01

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