JPS58122750A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS58122750A
JPS58122750A JP57004725A JP472582A JPS58122750A JP S58122750 A JPS58122750 A JP S58122750A JP 57004725 A JP57004725 A JP 57004725A JP 472582 A JP472582 A JP 472582A JP S58122750 A JPS58122750 A JP S58122750A
Authority
JP
Japan
Prior art keywords
film
mask
resist
layer
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57004725A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0123944B2 (sr
Inventor
Masuyuki Taki
滝　益志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57004725A priority Critical patent/JPS58122750A/ja
Publication of JPS58122750A publication Critical patent/JPS58122750A/ja
Publication of JPH0123944B2 publication Critical patent/JPH0123944B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP57004725A 1982-01-14 1982-01-14 半導体装置の製造方法 Granted JPS58122750A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57004725A JPS58122750A (ja) 1982-01-14 1982-01-14 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57004725A JPS58122750A (ja) 1982-01-14 1982-01-14 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS58122750A true JPS58122750A (ja) 1983-07-21
JPH0123944B2 JPH0123944B2 (sr) 1989-05-09

Family

ID=11591863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57004725A Granted JPS58122750A (ja) 1982-01-14 1982-01-14 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS58122750A (sr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62120714A (ja) * 1985-11-20 1987-06-02 Fujitsu Ltd デイジタル信号の歪補償回路
JPH03173430A (ja) * 1989-12-01 1991-07-26 Matsushita Electron Corp 配線の形成方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56122143A (en) * 1980-02-29 1981-09-25 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56122143A (en) * 1980-02-29 1981-09-25 Chiyou Lsi Gijutsu Kenkyu Kumiai Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62120714A (ja) * 1985-11-20 1987-06-02 Fujitsu Ltd デイジタル信号の歪補償回路
JPH03173430A (ja) * 1989-12-01 1991-07-26 Matsushita Electron Corp 配線の形成方法

Also Published As

Publication number Publication date
JPH0123944B2 (sr) 1989-05-09

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