JPS58184747A - 半導体用リ−ドピンのろう付方法 - Google Patents

半導体用リ−ドピンのろう付方法

Info

Publication number
JPS58184747A
JPS58184747A JP57068207A JP6820782A JPS58184747A JP S58184747 A JPS58184747 A JP S58184747A JP 57068207 A JP57068207 A JP 57068207A JP 6820782 A JP6820782 A JP 6820782A JP S58184747 A JPS58184747 A JP S58184747A
Authority
JP
Japan
Prior art keywords
brazing
lead
plated
ceramic substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57068207A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0226786B2 (2
Inventor
Hitoshi Tsuji
斉 辻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Kikinzoku Kogyo KK
Original Assignee
Tanaka Kikinzoku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Kikinzoku Kogyo KK filed Critical Tanaka Kikinzoku Kogyo KK
Priority to JP57068207A priority Critical patent/JPS58184747A/ja
Publication of JPS58184747A publication Critical patent/JPS58184747A/ja
Publication of JPH0226786B2 publication Critical patent/JPH0226786B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP57068207A 1982-04-23 1982-04-23 半導体用リ−ドピンのろう付方法 Granted JPS58184747A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57068207A JPS58184747A (ja) 1982-04-23 1982-04-23 半導体用リ−ドピンのろう付方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57068207A JPS58184747A (ja) 1982-04-23 1982-04-23 半導体用リ−ドピンのろう付方法

Publications (2)

Publication Number Publication Date
JPS58184747A true JPS58184747A (ja) 1983-10-28
JPH0226786B2 JPH0226786B2 (2) 1990-06-12

Family

ID=13367113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57068207A Granted JPS58184747A (ja) 1982-04-23 1982-04-23 半導体用リ−ドピンのろう付方法

Country Status (1)

Country Link
JP (1) JPS58184747A (2)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63310143A (ja) * 1987-06-12 1988-12-19 Ibiden Co Ltd 黒鉛製治具

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63310143A (ja) * 1987-06-12 1988-12-19 Ibiden Co Ltd 黒鉛製治具

Also Published As

Publication number Publication date
JPH0226786B2 (2) 1990-06-12

Similar Documents

Publication Publication Date Title
US3986255A (en) Process for electrically interconnecting chips with substrates employing gold alloy bumps and magnetic materials therein
CN1066578C (zh) 用于将集成电路芯片焊到芯片载体上的倒装片法
EP0114952B1 (en) Controlled braze joining of electronic packaging elements
US4675243A (en) Ceramic package for semiconductor devices
US4755631A (en) Apparatus for providing an electrical connection to a metallic pad situated on a brittle dielectric substrate
US4700879A (en) Method for manufacturing semiconductor power modules with an insulated contruction
EP0036113B1 (en) Solution for dissolving noble metal alloys which include tin and re-work method of removing said alloys from a substrate
CN100483707C (zh) 用于半导体器件的引线框架
JPS58184747A (ja) 半導体用リ−ドピンのろう付方法
US5700724A (en) Hermetically sealed package for a high power hybrid circuit
JPS61196546A (ja) フイルムキヤリヤ集積回路とその製造方法
JPH10242330A (ja) パワーモジュール用基板及びその製造法
JP3470789B2 (ja) 配線基板及びその製造方法
JP2696507B2 (ja) 複合ろう材のろう付方法
JP3049948B2 (ja) パッケージの製造方法
JPH0888297A (ja) 電子部品および電子部品接続構造体
JPH05259593A (ja) ＡｌＮ回路基板
JP3932343B2 (ja) 半導体用基板およびその製造方法
JPH04230063A (ja) 多層ヒートシンク
Puttlitz et al. Solder transfer technique for flip-chip and electronic assembly applications
JPS5838694A (ja) 半導体ダイボンデイング用はんだ
JPS58184749A (ja) 半導体用リ−ドピンのろう付方法
JPS58184750A (ja) 半導体用リ−ドピン
JPH06125162A (ja) セラミックス配線基板の製造方法
JP3594442B2 (ja) 半導体装置