JPS5873095A - ダイナミツク型メモリ装置 - Google Patents
ダイナミツク型メモリ装置Info
- Publication number
- JPS5873095A JPS5873095A JP56169887A JP16988781A JPS5873095A JP S5873095 A JPS5873095 A JP S5873095A JP 56169887 A JP56169887 A JP 56169887A JP 16988781 A JP16988781 A JP 16988781A JP S5873095 A JPS5873095 A JP S5873095A
- Authority
- JP
- Japan
- Prior art keywords
- switching transistor
- lines
- pit
- memory device
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56169887A JPS5873095A (ja) | 1981-10-23 | 1981-10-23 | ダイナミツク型メモリ装置 |
| US06/423,145 US4606010A (en) | 1981-10-23 | 1982-09-24 | Dynamic memory device |
| DE8282109152T DE3276456D1 (en) | 1981-10-23 | 1982-10-04 | Dynamic memory device |
| EP82109152A EP0077935B1 (de) | 1981-10-23 | 1982-10-04 | Dynamische Speicheranordnung |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56169887A JPS5873095A (ja) | 1981-10-23 | 1981-10-23 | ダイナミツク型メモリ装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5873095A true JPS5873095A (ja) | 1983-05-02 |
Family
ID=15894792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56169887A Pending JPS5873095A (ja) | 1981-10-23 | 1981-10-23 | ダイナミツク型メモリ装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4606010A (de) |
| EP (1) | EP0077935B1 (de) |
| JP (1) | JPS5873095A (de) |
| DE (1) | DE3276456D1 (de) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62153700U (de) * | 1986-03-20 | 1987-09-29 | ||
| JPS632197A (ja) * | 1986-06-20 | 1988-01-07 | Mitsubishi Electric Corp | 半導体記憶装置 |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4584672A (en) * | 1984-02-22 | 1986-04-22 | Intel Corporation | CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge |
| EP0169460B1 (de) * | 1984-07-26 | 1991-05-15 | Texas Instruments Incorporated | Dynamischer Speicheraufbau mit segmentierten und quasi-gefalteten Bitzeilen |
| US4908797A (en) * | 1984-07-26 | 1990-03-13 | Texas Instruments Incorporated | Dynamic memory array with quasi-folded bit lines |
| JPS6150284A (ja) * | 1984-08-17 | 1986-03-12 | Mitsubishi Electric Corp | シエアドセンスアンプ回路の駆動方法 |
| JPS6150283A (ja) * | 1984-08-17 | 1986-03-12 | Mitsubishi Electric Corp | シエアドセンスアンプの駆動回路 |
| EP0180054A3 (de) * | 1984-10-31 | 1988-05-11 | Texas Instruments Incorporated | Angepasste Struktur mit gefalzten Bitleitungsenden |
| EP0189699B1 (de) * | 1984-12-26 | 1992-09-30 | STMicroelectronics, Inc. | Festwertspeicher mit interdigitalen Bitzeilen |
| JPS6280897A (ja) * | 1985-10-04 | 1987-04-14 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPS6363196A (ja) * | 1986-09-02 | 1988-03-19 | Fujitsu Ltd | 半導体記憶装置 |
| JPS63104296A (ja) * | 1986-10-21 | 1988-05-09 | Nec Corp | 半導体記憶装置 |
| JPH0787239B2 (ja) * | 1986-11-18 | 1995-09-20 | 日本電気株式会社 | メモリ |
| US5189639A (en) * | 1987-11-26 | 1993-02-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having bit lines capable of partial operation |
| JPH01171195A (ja) * | 1987-12-25 | 1989-07-06 | Sony Corp | メモリ装置 |
| US5022009A (en) * | 1988-06-02 | 1991-06-04 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having reading operation of information by differential amplification |
| GB9007788D0 (en) * | 1990-04-06 | 1990-06-06 | Foss Richard C | Dynamic memory bitline precharge scheme |
| US5291437A (en) * | 1992-06-25 | 1994-03-01 | Texas Instruments Incorporated | Shared dummy cell |
| US5245578A (en) * | 1992-08-12 | 1993-09-14 | Micron Technology, Inc. | DRAM with a two stage voltage pull-down sense amplifier |
| JPH06333386A (ja) * | 1993-05-20 | 1994-12-02 | Fujitsu Ltd | 半導体記憶装置 |
| US5381368A (en) * | 1993-12-10 | 1995-01-10 | Micron Semiconductor, Inc. | Hardware implemented row copy enable mode for DRAMS to create repetitive backgrounds for video images or DRAM testing |
| JP4154006B2 (ja) * | 1996-12-25 | 2008-09-24 | 富士通株式会社 | 半導体記憶装置 |
| JP3824370B2 (ja) * | 1997-03-03 | 2006-09-20 | 富士通株式会社 | 半導体装置 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4045783A (en) * | 1976-04-12 | 1977-08-30 | Standard Microsystems Corporation | Mos one transistor cell ram having divided and balanced bit lines, coupled by regenerative flip-flop sense amplifiers, and balanced access circuitry |
| DE2919166C2 (de) * | 1978-05-12 | 1986-01-02 | Nippon Electric Co., Ltd., Tokio/Tokyo | Speichervorrichtung |
| JPS5577083A (en) * | 1978-12-04 | 1980-06-10 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor memory unit |
| US4363111A (en) * | 1980-10-06 | 1982-12-07 | Heightley John D | Dummy cell arrangement for an MOS memory |
-
1981
- 1981-10-23 JP JP56169887A patent/JPS5873095A/ja active Pending
-
1982
- 1982-09-24 US US06/423,145 patent/US4606010A/en not_active Expired - Lifetime
- 1982-10-04 EP EP82109152A patent/EP0077935B1/de not_active Expired
- 1982-10-04 DE DE8282109152T patent/DE3276456D1/de not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62153700U (de) * | 1986-03-20 | 1987-09-29 | ||
| JPS632197A (ja) * | 1986-06-20 | 1988-01-07 | Mitsubishi Electric Corp | 半導体記憶装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0077935A2 (de) | 1983-05-04 |
| DE3276456D1 (en) | 1987-07-02 |
| US4606010A (en) | 1986-08-12 |
| EP0077935B1 (de) | 1987-05-27 |
| EP0077935A3 (en) | 1985-08-07 |
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