JPS5986097U - ランダム・アクセス・メモリ - Google Patents

ランダム・アクセス・メモリ

Info

Publication number
JPS5986097U
JPS5986097U JP1983133758U JP13375883U JPS5986097U JP S5986097 U JPS5986097 U JP S5986097U JP 1983133758 U JP1983133758 U JP 1983133758U JP 13375883 U JP13375883 U JP 13375883U JP S5986097 U JPS5986097 U JP S5986097U
Authority
JP
Japan
Prior art keywords
pair
bit lines
fets
random access
cross
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983133758U
Other languages
English (en)
Other versions
JPS604320Y2 (ja
Inventor
リチヤ−ド・テイ−・デニスン
デヴイド・ビ−・ア−ドレ−
Original Assignee
インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション filed Critical インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション
Publication of JPS5986097U publication Critical patent/JPS5986097U/ja
Application granted granted Critical
Publication of JPS604320Y2 publication Critical patent/JPS604320Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356043—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Static Random-Access Memory (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は本考案に従うＲＡＭの１列を示した回路図、第
２図は本考案に従うＲＡＭに使用され得、　る最終ラッ
チ、データ出力駆動回路及び列選択回路の一一例を示す
回路図、第３図は２進゛１゛の読出しサイクル時に生じ
る種々の信号の波形図、第４図は２進“１′′の書込み
サイクル時の波形図、第５Ａ図及び第５Ｂ図は本考案と
共に使用され得る代表的な６素子セル及び４素子セルを
各々示す回路図、第６図はｍ列２行のＲＡＭの全体を示
す回路図である。 １０・・・・・・メモリ・セル、１２・・・・・・出力
ラッチ、１４・・・・・・データ出力駆動回路、１６・
・・・・・列選択回路、２０・＝−・・・感知ラッチ、
Ｄ・・・・・・デプレツショ　　ン・モードＦＥＴ１Ｅ
・・・・・・エンハンスメント舎モードＦＥＴ、ＷＬ・
・・・・・ワード線、ＢＳＬ、　ＢＳＲ−−−−−−ビ
ット線。

Claims (1)

  1. 【実用新案登録請求の範囲】 下記の（イ）乃至（ホ）を具備するランダム・アクセス
    Φメモリ。　　　　　　　　　　　　　　　　′（イ）
    ワード線が付勢されたときに一対のビット線を介して読
    出し又は書込みが行われる複数のメモリ・セル。　　　
    　　　　゛　　　　　　□（ロ）上記ビット線を初期設
    定するための手段。 ゛　　　（ハ）選択されたメモリ・セルから上記一対の
    ビット線へ読出された情報をラッチするためにバー１交
    差結合された一対の第１ＦＥＴと、バー２該第１ＦＥＴ
    の交差結合点及び電源の間に接続された一対の負荷素子
    と、バー３ゲートが上艷一対のビット線へ別々に直接接
    読され、読出し時に上記一対のビット線の間の差信号に
    応答して上記第１ＦＥＴをスイッチさせる一対の第２Ｆ
    ＥＴとを含む感知ラッチ回路。 に）上記一対の第１ＦＥＴの交差結合点から出力を取出
    すための手段。− （ホ）上記一対のビット線に接続された！込み手段。
JP1983133758U 1975-04-10 1983-08-31 ランダム・アクセス・メモリ Expired JPS604320Y2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/566,896 US3953839A (en) 1975-04-10 1975-04-10 Bit circuitry for enhance-deplete ram
US566896 1975-04-10

Publications (2)

Publication Number Publication Date
JPS5986097U true JPS5986097U (ja) 1984-06-11
JPS604320Y2 JPS604320Y2 (ja) 1985-02-06

Family

ID=24264860

Family Applications (2)

Application Number Title Priority Date Filing Date
JP51030922A Pending JPS51123530A (en) 1975-04-10 1976-03-23 Random access memory
JP1983133758U Expired JPS604320Y2 (ja) 1975-04-10 1983-08-31 ランダム・アクセス・メモリ

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP51030922A Pending JPS51123530A (en) 1975-04-10 1976-03-23 Random access memory

Country Status (4)

Country Link
US (1) US3953839A (ja)
JP (2) JPS51123530A (ja)
DE (1) DE2613543C2 (ja)
GB (1) GB1539890A (ja)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2457921C2 (de) * 1974-12-07 1976-12-09 Ibm Deutschland Verfahren und schaltungsanordnung zur erhoehung der schreibgeschwindigkeit in integrierten datenspeichern
JPS51111020A (en) * 1975-03-26 1976-10-01 Hitachi Ltd Semiconductor fixing memory equipment
US4168537A (en) * 1975-05-02 1979-09-18 Tokyo Shibaura Electric Co., Ltd. Nonvolatile memory system enabling nonvolatile data transfer during power on
US4025907A (en) * 1975-07-10 1977-05-24 Burroughs Corporation Interlaced memory matrix array having single transistor cells
JPS52110530A (en) * 1976-03-12 1977-09-16 Toshiba Corp Mos random access memory
JPS5342633A (en) * 1976-09-30 1978-04-18 Toshiba Corp Voltage sense circuit of semiconductor memory device
US4086659A (en) * 1977-02-28 1978-04-25 Xerox Corporation Control system for disk drive
US4123799A (en) * 1977-09-19 1978-10-31 Motorola, Inc. High speed IFGET sense amplifier/latch
US4247791A (en) * 1978-04-03 1981-01-27 Rockwell International Corporation CMOS Memory sense amplifier
US4224533A (en) * 1978-08-07 1980-09-23 Signetics Corporation Edge triggered flip flop with multiple clocked functions
US4255679A (en) * 1978-10-30 1981-03-10 Texas Instruments Incorporated Depletion load dynamic sense amplifier for MOS random access memory
US4207615A (en) * 1978-11-17 1980-06-10 Intel Corporation Non-volatile ram cell
JPS55132055A (en) * 1979-03-30 1980-10-14 Nec Corp Mos integrated circuit
JPS5833635B2 (ja) * 1979-12-25 1983-07-21 富士通株式会社 半導体記憶装置
JPS5856198B2 (ja) * 1980-09-25 1983-12-13 株式会社東芝 半導体記憶装置
JPS5819793A (ja) * 1981-07-27 1983-02-04 Toshiba Corp 半導体メモリ装置
US4494221A (en) * 1982-03-03 1985-01-15 Inmos Corporation Bit line precharging and equilibrating circuit
JPS6063786A (ja) * 1983-09-17 1985-04-12 Fujitsu Ltd センスアンプ
US4701644A (en) * 1986-08-13 1987-10-20 Harris Corporation Low power sense amplifier
US4843264A (en) * 1987-11-25 1989-06-27 Visic, Inc. Dynamic sense amplifier for CMOS static RAM
JPH02252194A (ja) * 1989-03-25 1990-10-09 Sony Corp 半導体メモリ装置
TW353535U (en) * 1990-11-19 1999-02-21 Hitachi Ltd Memory circuit improved in electrical characteristics
DE4111104C1 (ja) * 1991-04-05 1992-10-01 Siemens Ag, 8000 Muenchen, De
DE69228919T2 (de) * 1991-12-17 1999-08-26 Stmicroelectronics Tristate-Treiberschaltung für interne Datenbusleitungen
US6697896B1 (en) * 1999-12-31 2004-02-24 Intel Corporation Method and apparatus for implementing high speed signals using differential reference signals
US7041575B2 (en) * 2003-04-29 2006-05-09 Micron Technology, Inc. Localized strained semiconductor on insulator
US7273788B2 (en) * 2003-05-21 2007-09-25 Micron Technology, Inc. Ultra-thin semiconductors bonded on glass substrates
US7008854B2 (en) * 2003-05-21 2006-03-07 Micron Technology, Inc. Silicon oxycarbide substrates for bonded silicon on insulator
US7153753B2 (en) * 2003-08-05 2006-12-26 Micron Technology, Inc. Strained Si/SiGe/SOI islands and processes of making same
US20050041453A1 (en) * 2003-08-22 2005-02-24 Brazis Paul W. Method and apparatus for reading and writing to solid-state memory
US7544584B2 (en) * 2006-02-16 2009-06-09 Micron Technology, Inc. Localized compressive strained semiconductor
US8477550B2 (en) * 2010-05-05 2013-07-02 Stmicroelectronics International N.V. Pass-gated bump sense amplifier for embedded drams

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3671772A (en) * 1969-10-01 1972-06-20 Ibm Difference amplifier
US3882469A (en) * 1971-11-30 1975-05-06 Texas Instruments Inc Non-volatile variable threshold memory cell
DE2165729C3 (de) * 1971-12-30 1975-02-13 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithische, als Lese/Schreiboder als Festwertspeicher betreibbare Speicheranordnung
JPS4960843A (ja) * 1972-10-17 1974-06-13
US3838295A (en) * 1973-02-05 1974-09-24 Lockheed Electronics Co Ratioless mos sense amplifier
US3879621A (en) * 1973-04-18 1975-04-22 Ibm Sense amplifier
US3806898A (en) * 1973-06-29 1974-04-23 Ibm Regeneration of dynamic monolithic memories

Also Published As

Publication number Publication date
JPS51123530A (en) 1976-10-28
DE2613543A1 (de) 1976-10-21
GB1539890A (en) 1979-02-07
DE2613543C2 (de) 1983-10-27
JPS604320Y2 (ja) 1985-02-06
US3953839A (en) 1976-04-27

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