JPS62102546A - 混成集積回路装置の製造方法 - Google Patents

混成集積回路装置の製造方法

Info

Publication number
JPS62102546A
JPS62102546A JP60241873A JP24187385A JPS62102546A JP S62102546 A JPS62102546 A JP S62102546A JP 60241873 A JP60241873 A JP 60241873A JP 24187385 A JP24187385 A JP 24187385A JP S62102546 A JPS62102546 A JP S62102546A
Authority
JP
Japan
Prior art keywords
solder
integrated circuit
circuit device
hybrid integrated
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60241873A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0337305B2 (2
Inventor
Yoshitaka Fukuoka
義孝 福岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60241873A priority Critical patent/JPS62102546A/ja
Publication of JPS62102546A publication Critical patent/JPS62102546A/ja
Publication of JPH0337305B2 publication Critical patent/JPH0337305B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60—Seals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP60241873A 1985-10-29 1985-10-29 混成集積回路装置の製造方法 Granted JPS62102546A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60241873A JPS62102546A (ja) 1985-10-29 1985-10-29 混成集積回路装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60241873A JPS62102546A (ja) 1985-10-29 1985-10-29 混成集積回路装置の製造方法

Publications (2)

Publication Number Publication Date
JPS62102546A true JPS62102546A (ja) 1987-05-13
JPH0337305B2 JPH0337305B2 (2) 1991-06-05

Family

ID=17080796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60241873A Granted JPS62102546A (ja) 1985-10-29 1985-10-29 混成集積回路装置の製造方法

Country Status (1)

Country Link
JP (1) JPS62102546A (2)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6344407B1 (en) 1999-12-20 2002-02-05 Fujitsu Limited Method of manufacturing solder bumps and solder joints using formic acid

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6344407B1 (en) 1999-12-20 2002-02-05 Fujitsu Limited Method of manufacturing solder bumps and solder joints using formic acid
US6666369B2 (en) 1999-12-20 2003-12-23 Fujitsu Limited Semiconductor device manufacturing method, electronic parts mounting method and heating/melting process equipment

Also Published As

Publication number Publication date
JPH0337305B2 (2) 1991-06-05

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