JPS6232536U - - Google Patents

Info

Publication number
JPS6232536U
JPS6232536U JP1985124206U JP12420685U JPS6232536U JP S6232536 U JPS6232536 U JP S6232536U JP 1985124206 U JP1985124206 U JP 1985124206U JP 12420685 U JP12420685 U JP 12420685U JP S6232536 U JPS6232536 U JP S6232536U
Authority
JP
Japan
Prior art keywords
liquid crystal
crystal display
integrated circuit
mounting structure
display board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1985124206U
Other languages
English (en)
Other versions
JPH0219970Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985124206U priority Critical patent/JPH0219970Y2/ja
Publication of JPS6232536U publication Critical patent/JPS6232536U/ja
Application granted granted Critical
Publication of JPH0219970Y2 publication Critical patent/JPH0219970Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図ａは本考案のリード電極４を示す平面図
の略図で、第１図ｂは本考案の実装例を示す断面
の略図で、第１図ｃは本考案のリフロー前の状態
を示す略図である。第２図は従来の実装例を示す
断面の略図である。 １……ＩＣ、２……バンプ、３……ハンダバン
プ、３′……ハンダ流れ、４……リード電極、６
，６′……リード電極開孔部、７……リード電極
切りかき部。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 液晶表示板のリード電極部に集積回路（以
    下ＩＣと略す）をフエースダウンで実装するチツ
    プオングラスの実装構造において、ＩＣのパツド
    部に対向する液晶表示板のリード電極部に、１ケ
    以上の切りかき部を設置した事を特徴とした液晶
    表示板の集積回路実装構造。 (2) 前記ＩＣにハンダバンプを用いた事を特徴
    とする実用新案登録請求の範囲第１項記載の液晶
    表示板の集積回路実装構造。
JP1985124206U 1985-08-13 1985-08-13 Expired JPH0219970Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985124206U JPH0219970Y2 (ja) 1985-08-13 1985-08-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985124206U JPH0219970Y2 (ja) 1985-08-13 1985-08-13

Publications (2)

Publication Number Publication Date
JPS6232536U true JPS6232536U (ja) 1987-02-26
JPH0219970Y2 JPH0219970Y2 (ja) 1990-05-31

Family

ID=31016005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985124206U Expired JPH0219970Y2 (ja) 1985-08-13 1985-08-13

Country Status (1)

Country Link
JP (1) JPH0219970Y2 (ja)

Also Published As

Publication number Publication date
JPH0219970Y2 (ja) 1990-05-31

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