JPH0229541U - - Google Patents

Info

Publication number
JPH0229541U
JPH0229541U JP10752788U JP10752788U JPH0229541U JP H0229541 U JPH0229541 U JP H0229541U JP 10752788 U JP10752788 U JP 10752788U JP 10752788 U JP10752788 U JP 10752788U JP H0229541 U JPH0229541 U JP H0229541U
Authority
JP
Japan
Prior art keywords
chip
flip
flexible substrate
solder bumps
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10752788U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10752788U priority Critical patent/JPH0229541U/ja
Publication of JPH0229541U publication Critical patent/JPH0229541U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は、本考案のフエイスダウンしたＩＣチ
ツプを示す斜視図、第２図は、同ＩＣチツプの回
路形成面側を示す平面図、第３図は、本考案のフ
リツプチツプ実装状態を示す側面図、第４図は、
同外力による変形状態を示す側面図、第５図は、
従来のＩＣチツプの実装状態を示す側面図、第６
図は、同外力による変形状態を示す側面図である
。 １…Ｉチツプ、１１…回路形成面、１２，１３
，１４，１５…破砕溝、２，２，２，２…集積回
路、２Ａ，２Ｂ，２Ｃ，２Ｄ…チツプブロツク、
２１…配線、２２…半田バンプ、３…フレキシブ
ル基板、３１…ボンデングパツド。

Claims (1)

  1. 【実用新案登録請求の範囲】 集積回路を設けたＩＣチツプの回路形成面に設
    けた半田バンプをフエイスダウンしてフレキシブ
    ル基板のボンデングパツド上に搭載し、 前記半田バンプにより前記ＩＣチツプを前記フ
    レキシブル基板に接続させるフリツプチツプ実装
    において、 前記ＩＣチツプは、少なくとも一個以上の半田
    バンプを設けた集積回路を複数個配置し、前記集
    積回路相互を電気的に独立させるとともに、前記
    集積回路を有する各チツプブロツクを破砕溝によ
    り区分したことを特徴とするフリツプチツプ実装
    におけるＩＣチツプの構造。
JP10752788U 1988-08-15 1988-08-15 Pending JPH0229541U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10752788U JPH0229541U (ja) 1988-08-15 1988-08-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10752788U JPH0229541U (ja) 1988-08-15 1988-08-15

Publications (1)

Publication Number Publication Date
JPH0229541U true JPH0229541U (ja) 1990-02-26

Family

ID=31342022

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10752788U Pending JPH0229541U (ja) 1988-08-15 1988-08-15

Country Status (1)

Country Link
JP (1) JPH0229541U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010122728A1 (ja) * 2009-04-22 2010-10-28 シャープ株式会社 Ｉｃチップ、表示パネルおよび表示モジュール

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010122728A1 (ja) * 2009-04-22 2010-10-28 シャープ株式会社 Ｉｃチップ、表示パネルおよび表示モジュール

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