JPS6274344U - - Google Patents

Info

Publication number
JPS6274344U
JPS6274344U JP1985166796U JP16679685U JPS6274344U JP S6274344 U JPS6274344 U JP S6274344U JP 1985166796 U JP1985166796 U JP 1985166796U JP 16679685 U JP16679685 U JP 16679685U JP S6274344 U JPS6274344 U JP S6274344U
Authority
JP
Japan
Prior art keywords
island portion
island
periphery
hanging
frame structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985166796U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985166796U priority Critical patent/JPS6274344U/ja
Publication of JPS6274344U publication Critical patent/JPS6274344U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案に係るリードフレーム構体の一
実施例を示す平面図、第２図は第１図の―線
に沿う断面図、第３図は第１図のリードフレーム
構体を樹脂モールドした状態を示す平面図、第４
図は第３図の―線に沿う断面図、第５図は半
導体装置の製造における高温特性検査を説明する
ための説明図である。第６図はリードフレーム構
体の従来例を示す平面図、第７図は第６図のリー
ドフレーム構体を樹脂モールドした状態を示す平
面図、第８図は第７図の―線に沿う断面図で
ある。 １０……アイランド部、１１……吊りピン、１
２……リード、１４……貫通穴、１６……半導体
ペレツト、Ｂ……リードフレーム構体。

Claims (1)

  1. 【実用新案登録請求の範囲】 半導体ペレツトが固着マウントされるアイラン
    ド部と周辺から中央のアイランド部まで延びて該
    アイランド部を吊下支持する吊りピンと、アイラ
    ンド部の周辺部近傍まで延びてくる複数のリード
    とからなる金属製のリードフレーム構体において
    、 上記吊りピンからの通電により発生するジコー
    ル熱でアイランド部が発熱し易いように、アイラ
    ンド部に複数の貫通穴を形成したことを特徴とす
    るリードフレーム構体。
JP1985166796U 1985-10-30 1985-10-30 Pending JPS6274344U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985166796U JPS6274344U (ja) 1985-10-30 1985-10-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985166796U JPS6274344U (ja) 1985-10-30 1985-10-30

Publications (1)

Publication Number Publication Date
JPS6274344U true JPS6274344U (ja) 1987-05-13

Family

ID=31098112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985166796U Pending JPS6274344U (ja) 1985-10-30 1985-10-30

Country Status (1)

Country Link
JP (1) JPS6274344U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0283961A (ja) * 1988-09-20 1990-03-26 Hitachi Ltd 半導体装置の製造方法、それにより得られる半導体装置およびそれに用いる半導体ウエハ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0283961A (ja) * 1988-09-20 1990-03-26 Hitachi Ltd 半導体装置の製造方法、それにより得られる半導体装置およびそれに用いる半導体ウエハ

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