JPS6343887B2 - - Google Patents

Info

Publication number
JPS6343887B2
JPS6343887B2 JP58019142A JP1914283A JPS6343887B2 JP S6343887 B2 JPS6343887 B2 JP S6343887B2 JP 58019142 A JP58019142 A JP 58019142A JP 1914283 A JP1914283 A JP 1914283A JP S6343887 B2 JPS6343887 B2 JP S6343887B2
Authority
JP
Japan
Prior art keywords
silicon
single crystal
crystal silicon
porous
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58019142A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59144149A (ja
Inventor
Takanobu Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EASTERN STEEL
Original Assignee
EASTERN STEEL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EASTERN STEEL filed Critical EASTERN STEEL
Priority to JP58019142A priority Critical patent/JPS59144149A/ja
Publication of JPS59144149A publication Critical patent/JPS59144149A/ja
Publication of JPS6343887B2 publication Critical patent/JPS6343887B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/191—Preparing SOI wafers using full isolation by porous oxide silicon [FIPOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
JP58019142A 1983-02-08 1983-02-08 誘電体分離基板の製造方法 Granted JPS59144149A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58019142A JPS59144149A (ja) 1983-02-08 1983-02-08 誘電体分離基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58019142A JPS59144149A (ja) 1983-02-08 1983-02-08 誘電体分離基板の製造方法

Publications (2)

Publication Number Publication Date
JPS59144149A JPS59144149A (ja) 1984-08-18
JPS6343887B2 true JPS6343887B2 (mo) 1988-09-01

Family

ID=11991198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58019142A Granted JPS59144149A (ja) 1983-02-08 1983-02-08 誘電体分離基板の製造方法

Country Status (1)

Country Link
JP (1) JPS59144149A (mo)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60189238A (ja) * 1984-03-09 1985-09-26 Oki Electric Ind Co Ltd 半導体装置の製造方法
EP0225519A3 (en) * 1985-12-06 1989-12-06 Texas Instruments Incorporated High definition anodized sublayer boundary
US4910165A (en) * 1988-11-04 1990-03-20 Ncr Corporation Method for forming epitaxial silicon on insulator structures using oxidized porous silicon
JP3176072B2 (ja) * 1991-01-16 2001-06-11 キヤノン株式会社 半導体基板の形成方法
EP0553856B1 (en) * 1992-01-31 2002-04-17 Canon Kabushiki Kaisha Method of preparing a semiconductor substrate
KR950005464B1 (ko) * 1992-02-25 1995-05-24 삼성전자주식회사 반도체장치의 제조방법
US5331180A (en) * 1992-04-30 1994-07-19 Fujitsu Limited Porous semiconductor light emitting device

Also Published As

Publication number Publication date
JPS59144149A (ja) 1984-08-18

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