JPS636737U - - Google Patents

Info

Publication number
JPS636737U
JPS636737U JP1986101095U JP10109586U JPS636737U JP S636737 U JPS636737 U JP S636737U JP 1986101095 U JP1986101095 U JP 1986101095U JP 10109586 U JP10109586 U JP 10109586U JP S636737 U JPS636737 U JP S636737U
Authority
JP
Japan
Prior art keywords
semiconductor
package
semiconductor chip
bonded
tip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986101095U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986101095U priority Critical patent/JPS636737U/ja
Publication of JPS636737U publication Critical patent/JPS636737U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案による一実施例のアルミニウム
ワイヤの配線状態を示す側面図、第２図は従来技
術によるアルミニウムワイヤの配線状態を示す側
面図である。 図において、２は半導体チツプ、２ａはフアー
ストボンデイング部、３はワイヤ、３ａはネツク
、４はボンデイングツール、１１はインナーリー
ド、１１ａはセカンドボンデイング部、１１ｂは
段差、である。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体チツプ２を搭載する半導体パツケージで
    あつて、ワイヤ３とボンデイング接続される該半
    導体チツプ２近傍の該半導体パツケージの上部に
    形成された、複数のインナーリード１１の先端部
    に段差１１ｂを設けたことを特徴とする半導体セ
    ラミツクパツケージ。
JP1986101095U 1986-06-30 1986-06-30 Pending JPS636737U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986101095U JPS636737U (ja) 1986-06-30 1986-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986101095U JPS636737U (ja) 1986-06-30 1986-06-30

Publications (1)

Publication Number Publication Date
JPS636737U true JPS636737U (ja) 1988-01-18

Family

ID=30971526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986101095U Pending JPS636737U (ja) 1986-06-30 1986-06-30

Country Status (1)

Country Link
JP (1) JPS636737U (ja)

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