JPS6450437U - - Google Patents

Info

Publication number
JPS6450437U
JPS6450437U JP1987145454U JP14545487U JPS6450437U JP S6450437 U JPS6450437 U JP S6450437U JP 1987145454 U JP1987145454 U JP 1987145454U JP 14545487 U JP14545487 U JP 14545487U JP S6450437 U JPS6450437 U JP S6450437U
Authority
JP
Japan
Prior art keywords
semiconductor elements
blocking
sealed
utility
registration request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987145454U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987145454U priority Critical patent/JPS6450437U/ja
Publication of JPS6450437U publication Critical patent/JPS6450437U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例を示す図、第２図は
この一実施例の作用を説明するための図、第３図
は本考案の他の一実施例を示す図、第４図は従来
例を示す図、第５図はこの従来例の作用を説明す
るための図である。 １……半導体素子、４……アイランド、５……
電極、８……ダイボンデイング材、９……封止樹
脂、１１……インナーリード、１３……ワイヤ、
１５……接続端子、１６……クラツク、１７……
曲げ加工構造部、１９……曲げ加工構造部、２１
……封止樹脂、２３……凹部。

Claims (1)

    【実用新案登録請求の範囲】
  1. 複数の半導体素子を並設して封止してなる半導
    体素子の実装構造において、前記半導体素子の夫
    々の間に異常状態の伝播を遮断する遮断手段を設
    けたことを特徴とする半導体素子の実装構造。
JP1987145454U 1987-09-25 1987-09-25 Pending JPS6450437U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987145454U JPS6450437U (ja) 1987-09-25 1987-09-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987145454U JPS6450437U (ja) 1987-09-25 1987-09-25

Publications (1)

Publication Number Publication Date
JPS6450437U true JPS6450437U (ja) 1989-03-29

Family

ID=31414059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987145454U Pending JPS6450437U (ja) 1987-09-25 1987-09-25

Country Status (1)

Country Link
JP (1) JPS6450437U (ja)

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