JPS6457680A - Compound semiconductor integrated circuit device - Google Patents

Compound semiconductor integrated circuit device

Info

Publication number
JPS6457680A
JPS6457680A JP63057257A JP5725788A JPS6457680A JP S6457680 A JPS6457680 A JP S6457680A JP 63057257 A JP63057257 A JP 63057257A JP 5725788 A JP5725788 A JP 5725788A JP S6457680 A JPS6457680 A JP S6457680A
Authority
JP
Japan
Prior art keywords
layer
source
semiconductor
ohmic contact
drain electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63057257A
Other languages
English (en)
Other versions
JPH0750781B2 (ja
Inventor
Shigeru Kuroda
Takashi Mimura
Seiji Notomi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5725788A priority Critical patent/JPH0750781B2/ja
Publication of JPS6457680A publication Critical patent/JPS6457680A/ja
Publication of JPH0750781B2 publication Critical patent/JPH0750781B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)
JP5725788A 1987-03-18 1988-03-10 化合物半導体集積回路装置 Expired - Lifetime JPH0750781B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5725788A JPH0750781B2 (ja) 1987-03-18 1988-03-10 化合物半導体集積回路装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP6109787 1987-03-18
JP62-61097 1987-03-18
JP5725788A JPH0750781B2 (ja) 1987-03-18 1988-03-10 化合物半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS6457680A true JPS6457680A (en) 1989-03-03
JPH0750781B2 JPH0750781B2 (ja) 1995-05-31

Family

ID=26398273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5725788A Expired - Lifetime JPH0750781B2 (ja) 1987-03-18 1988-03-10 化合物半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPH0750781B2 (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02273942A (ja) * 1989-04-17 1990-11-08 Sumitomo Electric Ind Ltd 高電子移動度トランジスタおよびその製造方法
JPH06169065A (ja) * 1992-12-01 1994-06-14 Nec Corp 化合物半導体集積回路の製造方法
JPH07312373A (ja) * 1994-05-18 1995-11-28 Nec Corp 電界効果トランジスタ及びその製造方法
JP2007324263A (ja) * 2006-05-31 2007-12-13 Matsushita Electric Ind Co Ltd 電界効果トランジスタ及びその製造方法
JP2013175782A (ja) * 2005-12-13 2013-09-05 Cree Inc 注入領域および保護層を含む半導体デバイスおよびそれを形成する方法
JP2013179337A (ja) * 2006-11-06 2013-09-09 Cree Inc 埋込み層に低抵抗コンタクトを形成する打込み領域を含んだ半導体デバイスの製作方法および関連したデバイス

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59123272A (ja) * 1982-12-28 1984-07-17 Fujitsu Ltd 化合物半導体装置
JPS59172776A (ja) * 1983-03-23 1984-09-29 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS6050965A (ja) * 1983-08-31 1985-03-22 Toshiba Corp 電界効果トランジスタおよびその製造方法
JPS6050966A (ja) * 1983-08-31 1985-03-22 Toshiba Corp 電界効果トランジスタの製造方法
JPS6064430A (ja) * 1983-09-19 1985-04-13 Oki Electric Ind Co Ltd ＧａＡｓ系化合物半導体装置の製造方法
JPS63187666A (ja) * 1987-01-30 1988-08-03 Nippon Telegr & Teleph Corp <Ntt> 電界効果トランジスタの製法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59123272A (ja) * 1982-12-28 1984-07-17 Fujitsu Ltd 化合物半導体装置
JPS59172776A (ja) * 1983-03-23 1984-09-29 Oki Electric Ind Co Ltd 半導体装置の製造方法
JPS6050965A (ja) * 1983-08-31 1985-03-22 Toshiba Corp 電界効果トランジスタおよびその製造方法
JPS6050966A (ja) * 1983-08-31 1985-03-22 Toshiba Corp 電界効果トランジスタの製造方法
JPS6064430A (ja) * 1983-09-19 1985-04-13 Oki Electric Ind Co Ltd ＧａＡｓ系化合物半導体装置の製造方法
JPS63187666A (ja) * 1987-01-30 1988-08-03 Nippon Telegr & Teleph Corp <Ntt> 電界効果トランジスタの製法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02273942A (ja) * 1989-04-17 1990-11-08 Sumitomo Electric Ind Ltd 高電子移動度トランジスタおよびその製造方法
JPH06169065A (ja) * 1992-12-01 1994-06-14 Nec Corp 化合物半導体集積回路の製造方法
JPH07312373A (ja) * 1994-05-18 1995-11-28 Nec Corp 電界効果トランジスタ及びその製造方法
JP2013175782A (ja) * 2005-12-13 2013-09-05 Cree Inc 注入領域および保護層を含む半導体デバイスおよびそれを形成する方法
US9318594B2 (en) 2005-12-13 2016-04-19 Cree, Inc. Semiconductor devices including implanted regions and protective layers
JP2007324263A (ja) * 2006-05-31 2007-12-13 Matsushita Electric Ind Co Ltd 電界効果トランジスタ及びその製造方法
JP2013179337A (ja) * 2006-11-06 2013-09-09 Cree Inc 埋込み層に低抵抗コンタクトを形成する打込み領域を含んだ半導体デバイスの製作方法および関連したデバイス
US9984881B2 (en) 2006-11-06 2018-05-29 Cree, Inc. Methods of fabricating semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices

Also Published As

Publication number Publication date
JPH0750781B2 (ja) 1995-05-31

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