KR880010573A - 대규모 반도체 논리장치 - Google Patents

대규모 반도체 논리장치 Download PDF

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Publication number
KR880010573A
KR880010573A KR1019880000580A KR880000580A KR880010573A KR 880010573 A KR880010573 A KR 880010573A KR 1019880000580 A KR1019880000580 A KR 1019880000580A KR 880000580 A KR880000580 A KR 880000580A KR 880010573 A KR880010573 A KR 880010573A
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South Korea
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stage
circuits
buffer circuits
buffer
scale semiconductor
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KR1019880000580A
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KR900008023B1 (ko
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아키라 야마기와
도시히로 오카베
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미타 가츠시게
가부시키가이샤 히타치세이사쿠쇼
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Publication of KR880010573A publication Critical patent/KR880010573A/ko
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Microcomputers (AREA)

Abstract

내용 없음

Description

대규모 반도체 논리장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원 발명의 논리장치의 일실시예를 나타내는 도면.
제2도는 버퍼회로의 일례를 나타내는 회로도.
제3A도, 제3B도는 버퍼회로의 접속변경을 설명하는 도면.

Claims (4)

  1. 다른 위상을 가진 복수의 클록신호에 의해서 동작하고, 하나의 칩 위에 배치되는 대규모 반도체 논리장치에 있어서, (A)상기 복수의 클록신호를 받는 복수의 입력단과, (B)상기 복수의 입력단의 각각 접속되어 적어도 3단의 직렬접속으로 이루어지는 복수의 버퍼회로와, 제1단 버퍼회로는 상기 입력단의 근방에 배치되어 상기 입력단과 접속하고, 제2단 버퍼회로는 상기 칩의 중앙부에 배치되는 상기 제1단 버퍼회로와 접속하고, 그리고 (C)상기 복수의 버퍼회로를 통해서 상기 복수의 클록신호를 받는 복수의 부하회로로 이루어지며, 상기 복수의 부하회로는 상기 복수의 버퍼회로의 최종단 버퍼회로와 접속하고, 상기 제2단 버퍼회로와 상기 최종단 버퍼회로와의 사이에 있어서 각 단의 버퍼회로 사이를 모두 실질적으로 같은 선로 길이가 되도록 배선하고, 각 단의 버퍼회로에 접속하는 다음 단의 버퍼회로의 수를 모두 같게 하고, 각 최종단 버퍼회로와 각 부하회로와의 사이의 선로길이를 모두 실질적으로 같게 배선하고, 각 최종단 버퍼회로에 접속하는 상기 부하회로의 수를 모두 같게 하여 이루어지는 대규모 반도체 논리장치.
  2. 제1항에 있어서, 상기 복수의 버퍼회로는 직렬접속한 4단의 버퍼회로로 이루어지며, 상기 최종단 버퍼회로는 제4단 버퍼회로이며, 제2단 버퍼회로는 중심으로 하여 상기 칩을 4개의 에리어로 구분했을 때에 제3단 버퍼회로를 상기 각 구분한 4개의 에리어의 각각의 중앙부에 배치한 대규모 반도체 논리장치.
  3. 제1항에 있어서, 상기 복수의 버퍼회로의 적어도 상기 복수의 최종단 버퍼회로의 각각은 CMOS논리소자이고, 이 CMOS논리소자는 N-MOS트랜지스터와, P-MOS트랜지스터부를 N-MOS트랜지스터부보다 그 치수를 크게 하고, 따라서 CMOS논리소자의 상승과 하강 레스폰스를 실질적으로 동일하게 한 대규모 반도체 논리장치.
  4. 제1항 내지 제3항중 어느 한항에 있어서, 다른 상의 클록신호를 받는 버퍼회로끼리를 각 그룹으로 해서 근접 배치하고, 이 그룹은 다른 전원라인을 통해서 각 그룹의 버퍼회로에 급전되는 대규모 반도체 논리장치.
    ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880000580A 1987-02-23 1988-01-26 대규모 반도체 논리장치 Expired KR900008023B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62-37951 1987-02-23
JP87-37951 1987-02-23
JP62037951A JPH083773B2 (ja) 1987-02-23 1987-02-23 大規模半導体論理回路

Publications (2)

Publication Number Publication Date
KR880010573A true KR880010573A (ko) 1988-10-10
KR900008023B1 KR900008023B1 (ko) 1990-10-29

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KR1019880000580A Expired KR900008023B1 (ko) 1987-02-23 1988-01-26 대규모 반도체 논리장치

Country Status (4)

Country Link
US (1) US4812684A (ko)
JP (1) JPH083773B2 (ko)
KR (1) KR900008023B1 (ko)
CN (1) CN1009520B (ko)

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Also Published As

Publication number Publication date
CN88100886A (zh) 1988-09-07
US4812684A (en) 1989-03-14
JPS63205720A (ja) 1988-08-25
JPH083773B2 (ja) 1996-01-17
CN1009520B (zh) 1990-09-05
KR900008023B1 (ko) 1990-10-29

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