ATE393473T1 - Verfahren zur herstellung eines verbundsubstrats - Google Patents

Verfahren zur herstellung eines verbundsubstrats

Info

Publication number
ATE393473T1
ATE393473T1 AT04291472T AT04291472T ATE393473T1 AT E393473 T1 ATE393473 T1 AT E393473T1 AT 04291472 T AT04291472 T AT 04291472T AT 04291472 T AT04291472 T AT 04291472T AT E393473 T1 ATE393473 T1 AT E393473T1
Authority
AT
Austria
Prior art keywords
material compound
source substrate
thermal annealing
splitting area
predetermined splitting
Prior art date
Application number
AT04291472T
Other languages
English (en)
Inventor
Thibaut Maurice
Eric Guiot
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE393473T1 publication Critical patent/ATE393473T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Recrystallisation Techniques (AREA)
  • Laminated Bodies (AREA)
  • Polymers With Sulfur, Phosphorus Or Metals In The Main Chain (AREA)
  • Investigating Or Analysing Materials By Optical Means (AREA)
AT04291472T 2004-06-11 2004-06-11 Verfahren zur herstellung eines verbundsubstrats ATE393473T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04291472A EP1605505B1 (de) 2004-06-11 2004-06-11 Verfahren zur Herstellung eines Verbundsubstrats

Publications (1)

Publication Number Publication Date
ATE393473T1 true ATE393473T1 (de) 2008-05-15

Family

ID=34931172

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04291472T ATE393473T1 (de) 2004-06-11 2004-06-11 Verfahren zur herstellung eines verbundsubstrats

Country Status (5)

Country Link
US (2) US7217639B2 (de)
EP (1) EP1605505B1 (de)
JP (1) JP4343148B2 (de)
AT (1) ATE393473T1 (de)
DE (1) DE602004013292T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5044195B2 (ja) * 2006-11-10 2012-10-10 信越化学工業株式会社 Ｓｏｑ基板の製造方法
FR2914488B1 (fr) * 2007-03-30 2010-08-27 Soitec Silicon On Insulator Substrat chauffage dope
FR2915625B1 (fr) * 2007-04-27 2009-10-02 Soitec Silicon On Insulator Procede de transfert d'une couche epitaxiale
EP2103632A1 (de) * 2008-03-20 2009-09-23 Ineos Europe Limited Polimerisationsverfahren
US8698106B2 (en) * 2008-04-28 2014-04-15 Varian Semiconductor Equipment Associates, Inc. Apparatus for detecting film delamination and a method thereof
JP7782795B2 (ja) * 2021-10-04 2025-12-09 株式会社ノベルクリスタルテクノロジー 積層構造体、及び積層構造体の製造方法
FR3132787A1 (fr) * 2022-02-14 2023-08-18 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de suivi de fragilisation d’une interface entre un substrat et une couche et dispositif permettant un tel suivi

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09213652A (ja) * 1996-02-01 1997-08-15 Semiconductor Energy Lab Co Ltd レーザーアニール装置
US6033974A (en) * 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
US5877070A (en) 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US6166354A (en) * 1997-06-16 2000-12-26 Advanced Micro Devices, Inc. System and apparatus for in situ monitoring and control of annealing in semiconductor fabrication
FR2767416B1 (fr) 1997-08-12 1999-10-01 Commissariat Energie Atomique Procede de fabrication d'un film mince de materiau solide
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US6425971B1 (en) * 2000-05-10 2002-07-30 Silverbrook Research Pty Ltd Method of fabricating devices incorporating microelectromechanical systems using UV curable tapes
US20040087042A1 (en) * 2002-08-12 2004-05-06 Bruno Ghyselen Method and apparatus for adjusting the thickness of a layer of semiconductor material
EP1429381B1 (de) * 2002-12-10 2011-07-06 S.O.I.Tec Silicon on Insulator Technologies Verfahren zur Herstellung eines Verbundmaterials

Also Published As

Publication number Publication date
DE602004013292D1 (de) 2008-06-05
JP2006041488A (ja) 2006-02-09
US7217639B2 (en) 2007-05-15
US20050277269A1 (en) 2005-12-15
DE602004013292T2 (de) 2009-05-28
JP4343148B2 (ja) 2009-10-14
EP1605505B1 (de) 2008-04-23
US20070105246A1 (en) 2007-05-10
EP1605505A1 (de) 2005-12-14

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Legal Events

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