CN1143260A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN1143260A CN1143260A CN96108208A CN96108208A CN1143260A CN 1143260 A CN1143260 A CN 1143260A CN 96108208 A CN96108208 A CN 96108208A CN 96108208 A CN96108208 A CN 96108208A CN 1143260 A CN1143260 A CN 1143260A
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- soi layer
- impurity
- foreign ion
- soi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
Landscapes
- Element Separation (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR16405/95 | 1995-06-20 | ||
| KR1019950016405A KR0154292B1 (ko) | 1995-06-20 | 1995-06-20 | 반도체 소자의 소자분리막 형성방법 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1143260A true CN1143260A (zh) | 1997-02-19 |
Family
ID=19417576
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96108208A Pending CN1143260A (zh) | 1995-06-20 | 1996-06-19 | 半导体器件及其制造方法 |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH098123A (ja) |
| KR (1) | KR0154292B1 (ja) |
| CN (1) | CN1143260A (ja) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100308198B1 (ko) * | 1999-09-14 | 2001-11-07 | 윤종용 | 에스오아이 반도체 소자 분리 방법 |
| JP4175650B2 (ja) * | 2004-08-26 | 2008-11-05 | シャープ株式会社 | 半導体装置の製造方法 |
| US7875931B2 (en) | 2006-04-28 | 2011-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with isolation using impurity |
| JP5188095B2 (ja) * | 2006-04-28 | 2013-04-24 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| JP2008252066A (ja) * | 2007-03-06 | 2008-10-16 | Denso Corp | 半導体装置 |
| EP3823014B1 (en) * | 2019-11-15 | 2024-07-31 | Infineon Technologies AG | Devices including radio frequency devices and methods |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05218364A (ja) * | 1992-01-31 | 1993-08-27 | Canon Inc | 半導体基体の形成方法 |
| JP3277957B2 (ja) * | 1993-01-24 | 2002-04-22 | ソニー株式会社 | Soi半導体装置の製造方法 |
| JPH0774242A (ja) * | 1993-09-03 | 1995-03-17 | Fujitsu Ltd | 半導体装置及びその製造方法 |
-
1995
- 1995-06-20 KR KR1019950016405A patent/KR0154292B1/ko not_active Expired - Fee Related
-
1996
- 1996-06-13 JP JP8152112A patent/JPH098123A/ja active Pending
- 1996-06-19 CN CN96108208A patent/CN1143260A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| KR970003791A (ko) | 1997-01-29 |
| JPH098123A (ja) | 1997-01-10 |
| KR0154292B1 (ko) | 1998-12-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4752589A (en) | Process for the production of bipolar transistors and complementary MOS transistors on a common silicon substrate | |
| US7091079B2 (en) | Method of forming devices having three different operation voltages | |
| KR930010121B1 (ko) | 단일의 집적회로칩에 고압 및 저압 cmos 트랜지스터를 형성하는 공정 | |
| US7214591B2 (en) | Method of fabricating high-voltage MOS device | |
| US5329147A (en) | High voltage integrated flyback circuit in 2 μm CMOS | |
| US6159799A (en) | Method of manufacturing semiconductor device comprising high voltage regions and floating gates | |
| JPH058583B2 (ja) | ||
| JPH03201474A (ja) | 単一集積回路チップにおける垂直バイポーラトランジスタと高圧cmosの形成方法 | |
| JPH08222645A (ja) | 軽くドープしたドレイン領域を形成する方法 | |
| US5229308A (en) | Bipolar transistors with high voltage MOS transistors in a single substrate | |
| JPH04276653A (ja) | 集積回路デバイスの製造プロセス | |
| US5563080A (en) | Method of manufacturing a high voltage transistor in a semiconductor device | |
| JPH05251555A (ja) | Mos型集積回路の製造方法 | |
| US6396100B2 (en) | Efficient fabrication process for dual well type structures | |
| JP3470155B2 (ja) | 改良形バイポーラトランジスタ | |
| KR20040081048A (ko) | 반도체 장치 및 그 제조 방법 | |
| KR0154292B1 (ko) | 반도체 소자의 소자분리막 형성방법 | |
| US7939402B1 (en) | Semiconductor apparatus comprising bipolar transistors and metal oxide semiconductor transistors and manufacturing method | |
| JPS604596B2 (ja) | 相補形mos集積回路の製造方法 | |
| JP2002083879A (ja) | 半導体装置の製造方法 | |
| KR940010565B1 (ko) | Bicmos 반도체 소자 및 그 제조방법 | |
| RU2298856C2 (ru) | Способ изготовления мдп-транзистора на структуре кремний на сапфире | |
| KR100356827B1 (ko) | 반도체장치의 웰 및 그 형성방법 | |
| JPS63240058A (ja) | 半導体装置の製造方法 | |
| JPH0243348B2 (ja) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C01 | Deemed withdrawal of patent application (patent law 1993) | ||
| WD01 | Invention patent application deemed withdrawn after publication |