JPH0192143U - - Google Patents
Info
- Publication number
- JPH0192143U JPH0192143U JP1987189105U JP18910587U JPH0192143U JP H0192143 U JPH0192143 U JP H0192143U JP 1987189105 U JP1987189105 U JP 1987189105U JP 18910587 U JP18910587 U JP 18910587U JP H0192143 U JPH0192143 U JP H0192143U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- bonded
- chip
- semiconductor
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
- H10W72/247—Dispositions of multiple bumps
- H10W72/248—Top-view layouts, e.g. mirror arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/877—Bump connectors and die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
第1図は本考案の実施例の断面図、第2図は本
考案の他の実施例の断面図、第3図a,bはそれ
ぞれ従来例の断面図である。 図において、1は半導体チツプ、2は回路基板
、3は入出力信号線、4は電極、6はボンデイン
グワイヤ、7,22は半田バンプ、10は金属基
板、20は冷却板、21は半田層をそれぞれ示す
。
考案の他の実施例の断面図、第3図a,bはそれ
ぞれ従来例の断面図である。 図において、1は半導体チツプ、2は回路基板
、3は入出力信号線、4は電極、6はボンデイン
グワイヤ、7,22は半田バンプ、10は金属基
板、20は冷却板、21は半田層をそれぞれ示す
。
Claims (1)
- 【実用新案登録請求の範囲】 半導体チツプ1を、回路基板2にフリツプチツ
プボンデイングした半導体装置であつて、 金属よりなる冷却板20の下面が、半田層21
、或いは多数の半田バンプ22を介して、該半導
体チツプ1の底面に密着されてなることを特徴と
する半導体チツプの実装構造。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987189105U JPH0192143U (ja) | 1987-12-10 | 1987-12-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987189105U JPH0192143U (ja) | 1987-12-10 | 1987-12-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0192143U true JPH0192143U (ja) | 1989-06-16 |
Family
ID=31480160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987189105U Pending JPH0192143U (ja) | 1987-12-10 | 1987-12-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0192143U (ja) |
-
1987
- 1987-12-10 JP JP1987189105U patent/JPH0192143U/ja active Pending
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