JPH02290048A - 積層型半導体の実装方法 - Google Patents
積層型半導体の実装方法Info
- Publication number
- JPH02290048A JPH02290048A JP2013875A JP1387590A JPH02290048A JP H02290048 A JPH02290048 A JP H02290048A JP 2013875 A JP2013875 A JP 2013875A JP 1387590 A JP1387590 A JP 1387590A JP H02290048 A JPH02290048 A JP H02290048A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- stacked
- chip
- package
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
Landscapes
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2013875A JPH02290048A (ja) | 1989-02-15 | 1990-01-24 | 積層型半導体の実装方法 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3682289 | 1989-02-15 | ||
| JP1-36822 | 1989-02-15 | ||
| JP2013875A JPH02290048A (ja) | 1989-02-15 | 1990-01-24 | 積層型半導体の実装方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02290048A true JPH02290048A (ja) | 1990-11-29 |
| JPH0514427B2 JPH0514427B2 (de) | 1993-02-25 |
Family
ID=26349731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013875A Granted JPH02290048A (ja) | 1989-02-15 | 1990-01-24 | 積層型半導体の実装方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02290048A (de) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0320051A (ja) * | 1989-03-20 | 1991-01-29 | Seiko Epson Corp | 半導体装置 |
| JPH0531257U (ja) * | 1991-09-30 | 1993-04-23 | 船井電機株式会社 | 半導体の実装構造 |
| US6740981B2 (en) | 2000-03-27 | 2004-05-25 | Kabushiki Kaisha, Toshiba | Semiconductor device including memory unit and semiconductor module including memory units |
| US7466577B2 (en) | 2005-03-30 | 2008-12-16 | Hitachi, Ltd., Intellectual Property Group | Semiconductor storage device having a plurality of stacked memory chips |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6481348A (en) * | 1987-09-24 | 1989-03-27 | Hitachi Maxell | Manufacture of semiconductor device |
| JPH01184860A (ja) * | 1988-01-13 | 1989-07-24 | Hitachi Maxell Ltd | 半導体装置の製造方法 |
-
1990
- 1990-01-24 JP JP2013875A patent/JPH02290048A/ja active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6481348A (en) * | 1987-09-24 | 1989-03-27 | Hitachi Maxell | Manufacture of semiconductor device |
| JPH01184860A (ja) * | 1988-01-13 | 1989-07-24 | Hitachi Maxell Ltd | 半導体装置の製造方法 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0320051A (ja) * | 1989-03-20 | 1991-01-29 | Seiko Epson Corp | 半導体装置 |
| JPH0531257U (ja) * | 1991-09-30 | 1993-04-23 | 船井電機株式会社 | 半導体の実装構造 |
| US6740981B2 (en) | 2000-03-27 | 2004-05-25 | Kabushiki Kaisha, Toshiba | Semiconductor device including memory unit and semiconductor module including memory units |
| US7466577B2 (en) | 2005-03-30 | 2008-12-16 | Hitachi, Ltd., Intellectual Property Group | Semiconductor storage device having a plurality of stacked memory chips |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0514427B2 (de) | 1993-02-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6589810B1 (en) | BGA package and method of fabrication | |
| KR100319608B1 (ko) | 적층형 반도체 패키지 및 그 제조방법 | |
| US6028352A (en) | IC stack utilizing secondary leadframes | |
| US8053880B2 (en) | Stacked, interconnected semiconductor package | |
| US8785245B2 (en) | Method of manufacturing stack type semiconductor package | |
| US8110439B2 (en) | Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages | |
| US6552416B1 (en) | Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring | |
| EP0383296A2 (de) | Verfahren zum Herstellen einer Halbleiterbauelement-Packung | |
| US8653653B2 (en) | High density three dimensional semiconductor die package | |
| US20070262434A1 (en) | Interconnected ic packages with vertical smt pads | |
| US5061990A (en) | Semiconductor device and the manufacture thereof | |
| JP2002009236A (ja) | 多層半導体装置及びその製造方法 | |
| JPH1065096A (ja) | 積層型半導体パッケージ及びその製造方法 | |
| US9209159B2 (en) | Hidden plating traces | |
| US6791166B1 (en) | Stackable lead frame package using exposed internal lead traces | |
| US20090179318A1 (en) | Multi-channel stackable semiconductor device and method for fabricating the same, and stacking substrate applied to the semiconductor device | |
| CN218414563U (zh) | 封装结构、线路板及电子设备 | |
| JPH02290048A (ja) | 積層型半導体の実装方法 | |
| JPS63136642A (ja) | 二層式半導体集積回路 | |
| JPH06342874A (ja) | 高集積半導体装置 | |
| JPH02229461A (ja) | 半導体装置 | |
| JPS58178544A (ja) | リ−ドフレ−ム | |
| JPH0719165Y2 (ja) | マルチチップ構造 | |
| JP2685534B2 (ja) | フィルムキャリヤ | |
| KR20050059791A (ko) | 적층패키지의 제조방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |