JPH01139451U - - Google Patents

Info

Publication number
JPH01139451U
JPH01139451U JP1988036472U JP3647288U JPH01139451U JP H01139451 U JPH01139451 U JP H01139451U JP 1988036472 U JP1988036472 U JP 1988036472U JP 3647288 U JP3647288 U JP 3647288U JP H01139451 U JPH01139451 U JP H01139451U
Authority
JP
Japan
Prior art keywords
side walls
semiconductor element
bases
package
upper package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988036472U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988036472U priority Critical patent/JPH01139451U/ja
Publication of JPH01139451U publication Critical patent/JPH01139451U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案の一実施例の断面図、第２図ａ
は本考案の第２実施例の断面図、第２図ｂは同図
ａのＡ―Ａ矢視平面図、第３図は従来の半導体装
置の断面図である。 １……パツケージ基体、１ａ，７ａ……下部パ
ツケージ基体、１ｂ，７ｂ……上部パツケージ基
体、２……金属板、３，３ａ，３ｂ……ＩＣチツ
プ、４……ボンデイングワイヤ、５ａ，５ｂ，８
ａ，８ｂ……外部リード、６ａ，６ｂ……突起端
子、９……ろう材、１０……キヤツプ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 厚い側壁で囲まれたパツケージ基体の中央凹所
    に半導体素子が固着された下部および上部パツケ
    ージ基体を有し、かつ、前記下部および上部パツ
    ケージ基体の側壁上面が突き合うようにして重ね
    合わされ、前記それぞれの半導体素子の電極パツ
    ドにつながる外部リードが共に前記下部パツケー
    ジ基体の底面または側面から外部に引き出されて
    いることを特徴とする半導体装置。
JP1988036472U 1988-03-18 1988-03-18 Pending JPH01139451U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988036472U JPH01139451U (ja) 1988-03-18 1988-03-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988036472U JPH01139451U (ja) 1988-03-18 1988-03-18

Publications (1)

Publication Number Publication Date
JPH01139451U true JPH01139451U (ja) 1989-09-22

Family

ID=31263074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988036472U Pending JPH01139451U (ja) 1988-03-18 1988-03-18

Country Status (1)

Country Link
JP (1) JPH01139451U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005260138A (ja) * 2004-03-15 2005-09-22 Matsushita Electric Ind Co Ltd 基板装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005260138A (ja) * 2004-03-15 2005-09-22 Matsushita Electric Ind Co Ltd 基板装置

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