JPH03116033U - - Google Patents

Info

Publication number
JPH03116033U
JPH03116033U JP1990025560U JP2556090U JPH03116033U JP H03116033 U JPH03116033 U JP H03116033U JP 1990025560 U JP1990025560 U JP 1990025560U JP 2556090 U JP2556090 U JP 2556090U JP H03116033 U JPH03116033 U JP H03116033U
Authority
JP
Japan
Prior art keywords
chip
circuit board
cap
confirming
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990025560U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990025560U priority Critical patent/JPH03116033U/ja
Publication of JPH03116033U publication Critical patent/JPH03116033U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/073Connecting or disconnecting of die-attach connectors
    • H10W72/07351Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/321Structures or relative sizes of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/877Bump connectors and die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第1図aは、この考案の一実施例に係る半導体
装置の実装構造を側方より見た図、第1図bは、
同半導体装置の実装構造を上方から見た図、第2
図a、第2図b及び第2図cは、それぞれ順に同
半導体装置の実装構造の実装工程を説明する図、
第3図a及び第3図bは、それぞれ従来の半導体
装置の実装構造を説明する図である。 1……チツプ、1a……パツド、2……バンプ
、3……キヤツプ、3a……脚部、4……シリコ
ンゴム、5……接着剤、6……樹脂、A……配線
パターン、B……回路基板。

Claims (1)

    【実用新案登録請求の範囲】
  1. 回路基板上に搭載されるチツプと、このチツプ
    のパツド上に形成され、前記回路基板上の配線パ
    ターンに圧接されるバンプと、前記チツプを覆い
    、その脚部が前記回路基板に接着されるキヤツプ
    と、このキヤツプに設けられ、前記チツプの背面
    を押圧して、前記バンプと配線パターンとの圧接
    状態を保持する弾性体と、前記チツプの動作確認
    後、このチツプと前記回路基板との間に充填され
    る樹脂とよりなる半導体装置の実装構造。
JP1990025560U 1990-03-13 1990-03-13 Pending JPH03116033U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990025560U JPH03116033U (ja) 1990-03-13 1990-03-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990025560U JPH03116033U (ja) 1990-03-13 1990-03-13

Publications (1)

Publication Number Publication Date
JPH03116033U true JPH03116033U (ja) 1991-12-02

Family

ID=31528492

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990025560U Pending JPH03116033U (ja) 1990-03-13 1990-03-13

Country Status (1)

Country Link
JP (1) JPH03116033U (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01160028A (ja) * 1987-12-17 1989-06-22 Matsushita Electric Ind Co Ltd 電極の接続方法
JPH01192125A (ja) * 1988-01-27 1989-08-02 Sharp Corp 半導体装置の実装構造

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01160028A (ja) * 1987-12-17 1989-06-22 Matsushita Electric Ind Co Ltd 電極の接続方法
JPH01192125A (ja) * 1988-01-27 1989-08-02 Sharp Corp 半導体装置の実装構造

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