JPH03257535A - Multi-signal interruption circuit system - Google Patents

Abstract

PURPOSE:To easily decide the occurring position of a CPU interruption by outputting the position of the change signal that causes the interruption to a parallel input port led to the CPU in the number numerical value in the conditions where 2 or more change signals never produces the interruptions at one time. CONSTITUTION:The (n) sets of signal changing point detection circuits 11 - 1n detect the changes of the input signals and output these changes to an OR circuit 30 and a change signal position output circuit 50 as the changing signals. The circuit 30 outputs the changing signals to a CPU 20 as the interruption requiring signals. Then an interruption requirement is produced to the CPU 20 in the case of the change of either one of (n) sets of input signals. Meanwhile the circuit 50 receives the changing signals and converts the positions of the origins of transmission into the integer number values including the numerical values(1-n) and then turns these numerical values into the digital binary codes to output the changing signal position code of log2n to a parallel input port 40. In such a constitution, the CPU 20 can directly read the positions of the changing signals out of the port 40 based on the number numerical values of the digital codes at the reception of an interruption requiring signal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a multi-signal interrupt circuit system that receives signals that cause multiple interrupts as input and has the characteristic that two or more signals do not simultaneously cause interrupts. Regarding.

[Conventional technology]

Conventionally, this type of multi-signal interrupt circuit system detects the change point of input signals and sends an interrupt to the CPU via an OR circuit when interrupting the central processing unit (hereinafter referred to as f&CPU) at a change point of multiple signals. In addition to transmitting an interrupt request signal, the CPU processes the detection of a change signal using the output from a parallel input port that directly inputs an input signal.

FIG. 2 is a block diagram showing a conventional example.

As shown in FIG. 2, each of the n sets of input signals is connected to the parallel input port 80, and also connected to each of the n signal change point detection circuits 11 to 1n. The outputs of the signal change point detection circuits 11 to 1n are connected to an OR circuit 30, and this OR circuit 30 sends one interrupt request signal to the CPU.
Output to 90. The parallel input port 80 directly receives n sets of input signals, and the CPU 90 determines the change signal position by reading the change position of the parallel input port 80.

[Problem to be solved by the invention]

In the conventional multi-signal interrupt circuit system described above, the signal that causes the interrupt is directly input to the parallel input port, so the number of parallel input ports increases in proportion to the signal n that causes the interrupt, and the circuit scale increases. As the number of signals increases, the amount of processing by the CPU increases because the CPU determines which signal has changed and caused an interrupt.

An object of the present invention is to provide a multi-signal interrupt circuit that solves the above problems by providing a change signal position output circuit that converts a change signal into a position signal and inputs the position signal to a parallel input port.

[Means for solving problems]

The multi-signal interrupt circuit system according to the present invention is a multi-signal interrupt circuit system that inputs change signals that cause multiple interrupts and requests interrupts by multiple signals such that two or more change signals do not become interrupt causes at the same time. , n signal change point detection circuits are provided for each of n sets of input signals to detect the change points of the input signals and output change signals, and the outputs of these n signal change point detection circuits are inputted to form one signal change point detection circuit. a change signal position that outputs the position of an OR circuit that outputs an interrupt request signal and a signal change point detection circuit of one of the sources of the received change signal as a change signal position code of "rlog2n" when the change signal is received; It has an output circuit.

〔Example〕

Next, the present invention will be explained with reference to FIG.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, the same components as shown in FIG. 2 of the prior art described above are given the same numbers and symbols, and the explanation thereof will be omitted.

As shown in FIG. 1, the present invention includes an interrupt circuit that inputs n sets of input signals as interrupt requests to the central processing unit 220, and n signal change point detection circuits 11 to 1n, and their outputs as inputs. It has an OR circuit 30, a change signal level output circuit 50, and a parallel input port 40.

As in the prior art, the OR circuit 30 which receives the outputs of the signal change point detection circuits 11 to 1n outputs an interrupt request signal to the CPU 20.

The change signal position output circuit 50 is connected to the signal change point detection circuit 11.
When one change signal is received from ~1n, the source position of the received change signal is converted into a numerical value by digital encoding, and the change signal is sent to the parallel input port 40 by rlog2n'' output lines for n sets of positions. Connect as a position code. Therefore, the CPU 20 can directly read the changing signal value I from the parallel input port 40 in digital code.

Next, the operation will be explained with reference to FIG. The n sets of signal change point detection circuits 11 to in detect changes in the input signals and output them to the OR circuit 30 and the change signal position output circuit 50 as change signals.

The OR circuit 30 outputs the change signal to the CPU as an interrupt request signal.
Output to 20. Therefore, when any one of the n sets of input signals changes, an interrupt request to the CPU 20 is generated.

On the other hand, when the change signal position output circuit 50 receives the change signal, it converts the source position of the received change signal into an integer number value from 1 to n, encodes it in digital binary, and converts it into a '1o
g2n, outputs the change signal position code by the number 1 to the parallel input capo-40.

Therefore, when the CPU 20 receives the interrupt request signal, it can directly read the position of the change signal from the parallel input port 40 based on the numerical value of the digital code.

[Effects of the Invention] As explained above, in the case where there are a plurality of change signals that can cause an interrupt, the present invention can prevent two or more change signals from becoming a cause of an interrupt, provided that two or more change signals do not become a cause of an interrupt at the same time. By outputting the position of the change signal as a numerical value to the parallel input port to the CPU, the number of parallel input ports can be reduced, and the position of the CPU interrupt occurrence can be easily determined.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the multiple signal interrupt circuit system of the present invention, and FIG. 2 is a block diagram showing a conventional example. 11, ~1n... Signal change point detection circuit, 20... Central processing unit (CPU) = 30... OR circuit,
40...Parallel input port, 50...Change signal value I output circuit.

Claims (1)

[Claims] In a multiple signal interrupt circuit system that inputs change signals that cause multiple interrupts and requests interrupts by multiple signals such that two or more change signals do not simultaneously cause interrupts, n sets of interrupts are provided. n signal change point detection circuits are provided for each input signal to detect the change point of the input signal and output a change signal, and one interrupt request signal is generated by inputting the outputs of the n signal change point detection circuits. and a change signal position output circuit that outputs the position of one signal change point detection circuit that is the source of the received change signal as a change signal position code of "log_2n" when the change signal is received. A multi-signal interrupt circuit system characterized by having: