JPH0446544U - - Google Patents

Info

Publication number
JPH0446544U
JPH0446544U JP1990087609U JP8760990U JPH0446544U JP H0446544 U JPH0446544 U JP H0446544U JP 1990087609 U JP1990087609 U JP 1990087609U JP 8760990 U JP8760990 U JP 8760990U JP H0446544 U JPH0446544 U JP H0446544U
Authority
JP
Japan
Prior art keywords
lead
semiconductor pellet
semiconductor
inner end
pressed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990087609U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990087609U priority Critical patent/JPH0446544U/ja
Publication of JPH0446544U publication Critical patent/JPH0446544U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図は本考案にかかる半導体製造装置の斜視
図である。第２図は半導体ペレツトをマウントし
たリードフレームの斜視図、第３図は従来の半導
体装置の縦断面図である。 １……リードフレーム、２……フレーム、３…
…アイランド部、４……リード、４ａ……内端部
、５……タイバ、６……吊りピン、７……接着剤
、８……基板、９……半導体ペレツト、９ａ……
電極、１０……ヒータブロツク、１４……クラン
パ、１４ａ……窓部、１５……断熱材、１６……
セラミツク。

Claims (1)

  1. 【実用新案登録請求の範囲】 半導体ペレツトをマウントするアイランド部と
    、アイランド部の周辺に多数本平行に配置したリ
    ードを連結するタイバとを、吊りピンによつて連
    結一体化したリードフレムを、アイランド部およ
    びリードの内端部を露出させる窓部を形成した枠
    状のクランパにより、ヒータブロツク上に押圧固
    定し、半導体ペレツト上面の電極とリードの内端
    部とを、ワイヤボンデイングする半導体製造装置
    において、 上記クランパの押圧固定する面に、断熱材を介
    しセラミツクを設けたことを特徴とする半導体製
    造装置。
JP1990087609U 1990-08-21 1990-08-21 Pending JPH0446544U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990087609U JPH0446544U (ja) 1990-08-21 1990-08-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990087609U JPH0446544U (ja) 1990-08-21 1990-08-21

Publications (1)

Publication Number Publication Date
JPH0446544U true JPH0446544U (ja) 1992-04-21

Family

ID=31820096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990087609U Pending JPH0446544U (ja) 1990-08-21 1990-08-21

Country Status (1)

Country Link
JP (1) JPH0446544U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998001902A1 (en) * 1996-07-08 1998-01-15 Kabushiki Kaisha Toshiba Semiconductor component fixing jig, table for placement of semiconductor component and bonding apparatus
JP2017055031A (ja) * 2015-09-11 2017-03-16 トヨタ自動車株式会社 ワイヤ接続方法と端子

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998001902A1 (en) * 1996-07-08 1998-01-15 Kabushiki Kaisha Toshiba Semiconductor component fixing jig, table for placement of semiconductor component and bonding apparatus
JP2017055031A (ja) * 2015-09-11 2017-03-16 トヨタ自動車株式会社 ワイヤ接続方法と端子

Similar Documents

Publication Publication Date Title
JPH0446544U (ja)
JPH03101523U (ja)
JPH0235453U (ja)
JPS63149528U (ja)
JPS63188945U (ja)
JPS62204327U (ja)
JPH0350U (ja)
JPH0184431U (ja)
JPH02122440U (ja)
JPS6382950U (ja)
JPS6276535U (ja)
JPS63188944U (ja)
JPS63164224U (ja)
JPH0451143U (ja)
JPH0471019U (ja)
JPS63149551U (ja)
JPH0415122U (ja)
JPH0184449U (ja)
JPH0176043U (ja)
JPS62142847U (ja)
JPS6382949U (ja)
JPH0336151U (ja)
JPH01129849U (ja)
JPH0273743U (ja)
JPH0498857A (ja) 半導体装置用パッケージ