JPH0343732U - - Google Patents

Info

Publication number
JPH0343732U
JPH0343732U JP10468989U JP10468989U JPH0343732U JP H0343732 U JPH0343732 U JP H0343732U JP 10468989 U JP10468989 U JP 10468989U JP 10468989 U JP10468989 U JP 10468989U JP H0343732 U JPH0343732 U JP H0343732U
Authority
JP
Japan
Prior art keywords
metal substrate
semiconductor element
bonding pad
electrically connected
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10468989U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10468989U priority Critical patent/JPH0343732U/ja
Publication of JPH0343732U publication Critical patent/JPH0343732U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図は本考案による半導体素子の実装構造の
一実施例を示す断面図である。第2図は従来の半
導体素子の実装構造の一例を示す断面図である。 11……半導体素子、12……金属基板、13
……金属基材、15……導電パターン、15a…
…ボンデイングパツド、15b……電極、16…
…金線、17……導電性接着剤、18……金属ネ
ジ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 金属基板上に該金属基板の導電層を利用して設
    けられたボンデイングパツドと、該ボンデイング
    パツド上にダイボンデイングされた半導体素子と
    、上記金属基板の表面に形成された導電パターン
    でなる電極とを具備しており、該電極と半導体素
    子がワイヤボンデイングされることにより電気的
    に接続され且つ上記ボンデイングパツドと上記金
    属基板の金属基材とが導電部材を介して電気的に
    接続されていることを特徴とする、半導体素子の
    実装構造。
JP10468989U 1989-09-06 1989-09-06 Pending JPH0343732U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10468989U JPH0343732U (ja) 1989-09-06 1989-09-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10468989U JPH0343732U (ja) 1989-09-06 1989-09-06

Publications (1)

Publication Number Publication Date
JPH0343732U true JPH0343732U (ja) 1991-04-24

Family

ID=31653476

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10468989U Pending JPH0343732U (ja) 1989-09-06 1989-09-06

Country Status (1)

Country Link
JP (1) JPH0343732U (ja)

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