JPS55105358A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS55105358A
JPS55105358A JP1294579A JP1294579A JPS55105358A JP S55105358 A JPS55105358 A JP S55105358A JP 1294579 A JP1294579 A JP 1294579A JP 1294579 A JP1294579 A JP 1294579A JP S55105358 A JPS55105358 A JP S55105358A
Authority
JP
Japan
Prior art keywords
embedded layer
cell array
parasitic capacity
integration
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1294579A
Other languages
Japanese (ja)
Other versions
JPH0133947B2 (en
Inventor
Yasumasa Tsunekawa
Kenji Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1294579A priority Critical patent/JPS55105358A/en
Publication of JPS55105358A publication Critical patent/JPS55105358A/en
Publication of JPH0133947B2 publication Critical patent/JPH0133947B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE: To reduce the parasitic capacity and to improve the extent of integration and the performance by making the depth of embedded layer of the memory cell array shallower than that of the peripheral circuit.
CONSTITUTION: The width of the channel stopper is determined by the manufacturing technique independently of the depth of embedded layer, the distance between elements can be reduced in the case of a shallow embeded layer as compared with a deep one, a cell array with a high integration can be obtained. Also the shallower the embedded layer, the less the cross-sectional area of junction, and the parasitic capacity is reduced. In this way, a memory cell array with higher integration and less parasitic capacity can be obtained by shallowing the embedded layer of the cell.
COPYRIGHT: (C)1980,JPO&Japio
JP1294579A 1979-02-07 1979-02-07 Semiconductor memory Granted JPS55105358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1294579A JPS55105358A (en) 1979-02-07 1979-02-07 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1294579A JPS55105358A (en) 1979-02-07 1979-02-07 Semiconductor memory

Publications (2)

Publication Number Publication Date
JPS55105358A true JPS55105358A (en) 1980-08-12
JPH0133947B2 JPH0133947B2 (en) 1989-07-17

Family

ID=11819412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1294579A Granted JPS55105358A (en) 1979-02-07 1979-02-07 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS55105358A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5863163A (en) * 1981-10-12 1983-04-14 Nec Corp Semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147284A (en) * 1975-06-13 1976-12-17 Fujitsu Ltd Manufacturing process of semiconductor device
JPS51147968A (en) * 1975-06-14 1976-12-18 Fujitsu Ltd Method of manufacturing semiconductor device
JPS5368182A (en) * 1976-11-30 1978-06-17 Fujitsu Ltd Production of semiconductor memory device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147284A (en) * 1975-06-13 1976-12-17 Fujitsu Ltd Manufacturing process of semiconductor device
JPS51147968A (en) * 1975-06-14 1976-12-18 Fujitsu Ltd Method of manufacturing semiconductor device
JPS5368182A (en) * 1976-11-30 1978-06-17 Fujitsu Ltd Production of semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5863163A (en) * 1981-10-12 1983-04-14 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0133947B2 (en) 1989-07-17

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