JPS5844859U - 混成集積回路 - Google Patents

混成集積回路

Info

Publication number
JPS5844859U
JPS5844859U JP1981139785U JP13978581U JPS5844859U JP S5844859 U JPS5844859 U JP S5844859U JP 1981139785 U JP1981139785 U JP 1981139785U JP 13978581 U JP13978581 U JP 13978581U JP S5844859 U JPS5844859 U JP S5844859U
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
substrate
conductive film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981139785U
Other languages
English (en)
Inventor
力武　恭一
小山　正孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1981139785U priority Critical patent/JPS5844859U/ja
Publication of JPS5844859U publication Critical patent/JPS5844859U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図乃至第５図は本考案にかかる実施例の混成集積回
路の製造工程説明図であって、第５図は本考案にかかる
実施例の混成集積回路の断面図、第６図はその配線用導
体の構成を示す断面図である。 １．８・・・・・・コンタクトホール、２，９・・・・
・・耐熱性樹脂フィルム、３，１０・・・・・・熱可塑
性樹脂層、５・・・・・・半導体ＩＣチップ、６・・・
・・・内部配線リード、１１・・・・・・金属フレーム
、１２・・・・・・受動素子、１３・・・・・・配線用
導体膜、１５・・・・・・混成集積回路用半導体ＩＣチ
ップ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 表面に熱可塑性樹脂層を設けた耐熱性樹脂フィルム基板
    に複数個の半導体素子を熱圧着し、該素子間の電極を導
    体膜で連結して成る混成集積回路において、半導体ＩＣ
    チップは予め前記フィルム基板と同様な基板に熱圧着し
    たのち導体膜でリードを形成しておき、前記受動素子を
    搭載した基板の導体膜に半田リフロー法によって連結し
    たことを特徴とする混成集積回路。
JP1981139785U 1981-09-22 1981-09-22 混成集積回路 Pending JPS5844859U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981139785U JPS5844859U (ja) 1981-09-22 1981-09-22 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981139785U JPS5844859U (ja) 1981-09-22 1981-09-22 混成集積回路

Publications (1)

Publication Number Publication Date
JPS5844859U true JPS5844859U (ja) 1983-03-25

Family

ID=29932965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981139785U Pending JPS5844859U (ja) 1981-09-22 1981-09-22 混成集積回路

Country Status (1)

Country Link
JP (1) JPS5844859U (ja)

Similar Documents

Publication Publication Date Title
JP2840317B2 (ja) 半導体装置およびその製造方法
JP2595803B2 (ja) 混成集積回路装置
JPH0661404A (ja) 半導体装置
JP2784209B2 (ja) 半導体装置
JPH04269841A (ja) 半導体装置
JPS5883150U (ja) 半導体集積回路装置
JP2599290Y2 (ja) ハイブリッドｉｃ
JPS6127338U (ja) 混成集積回路装置
JPS5923432Y2 (ja) 半導体装置
JPS60227492A (ja) 電子回路ブロツク
JPH07170050A (ja) 半導体装置
JPH05211246A (ja) リードレスチップキャリア型半導体装置
JPH02229460A (ja) リードフレームとそれを用いた半導体装置
JPS5822741U (ja) 半導体パツケ−ジ
JPS59192862U (ja) 混成集積回路
JPS5895046U (ja) 混成集積回路
JPS6387889U (ja)
JPS6142843U (ja) 半導体装置
JPS58120647U (ja) 混成集積回路
JPS6042760U (ja) 半導体装置
JPS60149166U (ja) 混成集積回路装置
JPS6079771U (ja) 多層配線基板
JPS59180427U (ja) ハイブリツド集積回路装置
JPS588953U (ja) 半導体装置
JPS6169850U (ja)