JPS6025145U - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6025145U
JPS6025145U JP1983115317U JP11531783U JPS6025145U JP S6025145 U JPS6025145 U JP S6025145U JP 1983115317 U JP1983115317 U JP 1983115317U JP 11531783 U JP11531783 U JP 11531783U JP S6025145 U JPS6025145 U JP S6025145U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor element
lowered
semiconductor
honding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983115317U
Other languages
English (en)
Inventor
谷浦 隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1983115317U priority Critical patent/JPS6025145U/ja
Publication of JPS6025145U publication Critical patent/JPS6025145U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第1図は従来の装置の断面図、第2図、第3図は本考案
の実施例の断面図である。 1・・・・・・半導体素子、2・・・・・・外部引き出
し用リード(封止部内はステッチ)、3・・・・・・ア
イランド(半導体素子搭載部)、3′・・・凹部、4・
・・・・・封止樹脂。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体素子が搭載されるアイランド部において、半導体
    素子搭載部の周辺が折り曲けられて低くなっており、こ
    の5低くなった面の上をホンディング線がまたいている
    ことを特徴とする半導体装置。
JP1983115317U 1983-07-25 1983-07-25 半導体装置 Pending JPS6025145U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983115317U JPS6025145U (ja) 1983-07-25 1983-07-25 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983115317U JPS6025145U (ja) 1983-07-25 1983-07-25 半導体装置

Publications (1)

Publication Number Publication Date
JPS6025145U true JPS6025145U (ja) 1985-02-20

Family

ID=30266236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983115317U Pending JPS6025145U (ja) 1983-07-25 1983-07-25 半導体装置

Country Status (1)

Country Link
JP (1) JPS6025145U (ja)

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