JPS6413140U - - Google Patents
Info
- Publication number
- JPS6413140U JPS6413140U JP1987107984U JP10798487U JPS6413140U JP S6413140 U JPS6413140 U JP S6413140U JP 1987107984 U JP1987107984 U JP 1987107984U JP 10798487 U JP10798487 U JP 10798487U JP S6413140 U JPS6413140 U JP S6413140U
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead frame
- semiconductor chip
- back surface
- chamfered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図は本考案の実施例に係る半導体装置の断
面図、第２図ａ，ｂは、夫々異なる従来例の断面
図、内部構造を示す斜視図である。 １１……半導体チツプ、１２……リードフレー
ム、１２ａ……面取り、１３……外装樹脂、１３
ａ……成型ゲート。
面図、第２図ａ，ｂは、夫々異なる従来例の断面
図、内部構造を示す斜視図である。 １１……半導体チツプ、１２……リードフレー
ム、１２ａ……面取り、１３……外装樹脂、１３
ａ……成型ゲート。
Claims (1)
- 放熱板兼用のリードフレームの主面に半導体チ
ツプを搭載し、該半導体チツプを搭載した前記リ
ードフレームの裏面に被着する樹脂膜を薄膜状に
して外装樹脂をトランスフア成型してなる樹脂封
止型半導体装置において、前記リードフレーム裏
面に樹脂流れを良くするための面取りが施された
ことを特徴とする樹脂封止型半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987107984U JPS6413140U (ja) | 1987-07-14 | 1987-07-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987107984U JPS6413140U (ja) | 1987-07-14 | 1987-07-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6413140U true JPS6413140U (ja) | 1989-01-24 |
Family
ID=31342895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987107984U Pending JPS6413140U (ja) | 1987-07-14 | 1987-07-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6413140U (ja) |
-
1987
- 1987-07-14 JP JP1987107984U patent/JPS6413140U/ja active Pending