JPS6448039U - - Google Patents

Info

Publication number
JPS6448039U
JPS6448039U JP1987143097U JP14309787U JPS6448039U JP S6448039 U JPS6448039 U JP S6448039U JP 1987143097 U JP1987143097 U JP 1987143097U JP 14309787 U JP14309787 U JP 14309787U JP S6448039 U JPS6448039 U JP S6448039U
Authority
JP
Japan
Prior art keywords
ceramic layer
patterned
ceramic
inner lead
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987143097U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987143097U priority Critical patent/JPS6448039U/ja
Publication of JPS6448039U publication Critical patent/JPS6448039U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図ａはこの考案の一実施例の構造を示す断
面図、第１図ｂは第１図ａのパツケージにおける
パターンセラミツク層表面のインナーリードパタ
ーンの配列状態の一例を示す平面図、第２図ａは
従来のセラミツク積層型パツケージの一例の構造
を示す断面図、第２図ｂは第２図ａのパツケージ
におけるパターンセラミツク層表面のインナーリ
ードパターンの配列状態の一例を示す平面図であ
る。 １ａ……セラミツク積層型パツケージ、１１…
…底部セラミツク層、１２ａ，１２ｂ……パター
ンセラミツク層、１３ａ，１３ｂ……インナーリ
ードパターン、１４……上部セラミツク層、２…
…半導体ペレツト、３……ワイヤ、４……セラミ
ツクの蓋板、５……高温ハンダ、６ａ，６ｂ……
外部リード、７……銀ろう。なお各図中同一符号
は同一または相当する部分を示す。

Claims (1)

    【実用新案登録請求の範囲】
  1. 焼結前のセラミツク板が積み重ねられて焼結さ
    れ形成されるセラミツク積層型パツケージで、半
    導体ペレツトが取付けられる底部セラミツク層と
    、該底部セラミツク層のペレツト取付け領域を除
    く部分に結合した表面に周辺にまで延びるインナ
    ーリードパターンを有する第１のパターンセラミ
    ツク層と、該第１のパターンセラミツク層のワイ
    ヤボンド領域を除く部分に結合した表面に周辺に
    まで延びるインナーリードパターンを有する第２
    のパターンセラミツク層と、該第２のパターンセ
    ラミツク層のワイヤボンド領域を除く部分に結合
    した表面にセラミツクの蓋板が高温ハンダ封着さ
    れる上部セラミツク層とからなり、上記第２のパ
    ターンセラミツク層の外周面に取付けられる該層
    表面の各インナーリードパターンに対する外部リ
    ードが上記第１のパターンセラミツク層の外周面
    に取付けられる該層表面の各インナーリードパタ
    ーンに対する外部リードの外側にくる半導体装置
    用セラミツク積層型パツケージ。
JP1987143097U 1987-09-21 1987-09-21 Pending JPS6448039U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987143097U JPS6448039U (ja) 1987-09-21 1987-09-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987143097U JPS6448039U (ja) 1987-09-21 1987-09-21

Publications (1)

Publication Number Publication Date
JPS6448039U true JPS6448039U (ja) 1989-03-24

Family

ID=31409612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987143097U Pending JPS6448039U (ja) 1987-09-21 1987-09-21

Country Status (1)

Country Link
JP (1) JPS6448039U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0396047U (ja) * 1990-01-22 1991-10-01
JPH06112359A (ja) * 1992-09-30 1994-04-22 Kyocera Corp 電子部品搭載用回路基板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5561041A (en) * 1978-10-30 1980-05-08 Mitsubishi Electric Corp Packaging device for semiconductor integrated circuit
JPS55143045A (en) * 1979-04-26 1980-11-08 Mitsubishi Electric Corp Semiconductor device
JPS5651851A (en) * 1979-10-05 1981-05-09 Hitachi Ltd Semiconductor device
JPS56126948A (en) * 1980-03-12 1981-10-05 Hitachi Ltd Highly integrated semiconductor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5561041A (en) * 1978-10-30 1980-05-08 Mitsubishi Electric Corp Packaging device for semiconductor integrated circuit
JPS55143045A (en) * 1979-04-26 1980-11-08 Mitsubishi Electric Corp Semiconductor device
JPS5651851A (en) * 1979-10-05 1981-05-09 Hitachi Ltd Semiconductor device
JPS56126948A (en) * 1980-03-12 1981-10-05 Hitachi Ltd Highly integrated semiconductor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0396047U (ja) * 1990-01-22 1991-10-01
JPH06112359A (ja) * 1992-09-30 1994-04-22 Kyocera Corp 電子部品搭載用回路基板

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