US6750508B2 - Power semiconductor switching element provided with buried electrode - Google Patents

Power semiconductor switching element provided with buried electrode Download PDF

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Publication number
US6750508B2
US6750508B2 US09/892,545 US89254501A US6750508B2 US 6750508 B2 US6750508 B2 US 6750508B2 US 89254501 A US89254501 A US 89254501A US 6750508 B2 US6750508 B2 US 6750508B2
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layer
trench
drift layer
insulating film
electrode
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US20020030237A1 (en
Inventor
Ichiro Omura
Wataru Saito
Tsuneo Ogura
Hiromichi Ohashi
Yoshihiko Saito
Kenichi Tokano
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Toshiba Corp
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Toshiba Corp
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Priority to US10/770,014 priority Critical patent/US7067870B2/en
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Definitions

  • the present invention relates to a power semiconductor switching element and, more particularly, to a semiconductor element having a low ON resistance.
  • power MOSFETs power MOSFETs
  • power MOSFETs power MOSFETs
  • FIG. 44 is a sectional view of a conventional vertical power MOSFET.
  • an n-type drift layer 112 is formed on one surface of an n-type semiconductor substrate 111 by epitaxial growth.
  • P-type well layers 113 for MOS formation are selectively formed in the surface of the drift layer 112 .
  • N-type source layers 114 are selectively formed in the surfaces of the well layers 113 .
  • Trenches 115 are formed to reach the inside of the drift layer 112 from the surface of the source layers 114 through the well layers 113 .
  • Gate electrodes 119 are formed in the trenches 115 through silicon oxide films 118 .
  • a drain electrode 120 is formed on the other surface of the semiconductor substrate 111 .
  • Source electrodes 121 connected to the source layers 114 and well layers 113 are formed on the well layers 113 .
  • Vb is the static breakdown voltage
  • R on is the ON resistance
  • the upper characteristic limit can be exceeded by burying a p-type diffusion layer in the drift layer 112 . According to a structure having this buried diffusion layer, the ON resistance certainly decreases. However, since the junction distance (area) is long (large), the junction capacitance is large, resulting in slow switching. For the same reason, too many carriers are injected into a reverse-conducting diode incorporated in an element, and hence the element tends to break during a period of reverse recovery.
  • a semiconductor element comprising a semiconductor substrate of a first conductivity type having a first major surface and a second major surface opposing the first major surface, a drift layer of the first conductivity type formed on the first major surface of the semiconductor substrate, a well layer of a second conductivity type selectively formed in a surface of the drift layer, a source layer of the first conductivity type selectively formed in a surface of the well layer, a trench formed to reach at least an inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film, a first main electrode formed on the second major surface of the semiconductor substrate, and a second main electrode connected to the source layer and the well layer.
  • a semiconductor element comprising a semiconductor substrate of a first conductivity type having a first major surface and a second major surface opposing the first major surface, a drift layer of the first conductivity type formed on the first major surface of the semiconductor substrate, a well layer of a second conductivity type selectively formed in a surface of the drift layer, a source layer of the first conductivity type selectively formed in a surface of the well layer, a trench formed to reach at least an inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed through a first insulating film in a region extending from the trench of the drift layer to a bottom surface of the trench, a control electrode formed in a region extending from the source layer to the drift layer through the well layer in the trench to be insulated from the buried electrode through a second insulating film, a first main electrode formed on the second major surface of the semiconductor substrate, and a second main electrode connected to the source layer and the well layer.
  • a semiconductor element comprising a semiconductor substrate of a first conductivity type having a first major surface and a second major surface opposing the first major surface, a drift layer of the first conductivity type formed on the first major surface of the semiconductor substrate, a trench formed to reach at least an inside of the drift layer from a surface of the drift layer, a buried electrode formed in the trench through a first insulating film, a well layer of a second conductivity type selectively formed in a surface of the drift layer between the trenches, a source layer of the first conductivity type selectively formed in a surface of the well layer, a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film, a first main electrode formed on the second major surface of the semiconductor substrate, and a second main electrode connected to the source layer and the well layer.
  • a semiconductor element comprising a semiconductor substrate of a first conductivity type having a first major surface and a second major surface opposing the first major surface, a drift layer of the first conductivity type formed on the first major surface of the semiconductor substrate, a well layer of a second conductivity type selectively formed in a surface of the drift layer, a first trench formed to reach at least an inside of the drift layer through the well layer, a buried electrode formed in the first trench through a first insulating film, a source layer of the first conductivity type selectively formed in a surface of the well layer between the first trenches, a second trench formed to reach an inside of the drift layer from a surface of the source layer through the well layer, a control electrode formed in the second trench through a second insulating film, a first main electrode formed on the second major surface of the semiconductor substrate, and a second main electrode connected to the source layer and the well layer.
  • a semiconductor element comprising a semiconductor substrate of a first conductivity type having a first major surface and a second major surface opposing the first major surface, a drift layer of the first conductivity type formed on the first major surface of the semiconductor substrate, a well layer of a second conductivity type selectively formed in a surface of the drift layer, a buried diffusion layer of the second conductivity type formed to reach at least an inside of the drift layer through the well layer, a source layer of the first conductivity type selectively formed in a surface of the well layer between the buried diffusion layers, a trench formed to reach an inside of the drift layer from a surface of the source layer through the well layer, a control electrode formed in the trench through an insulating film, a first main electrode formed on the second major surface of the semiconductor substrate, and a second main electrode connected to the source layer and the well layer.
  • a semiconductor element comprising a semiconductor substrate of a first conductivity type having a first major surface and a second major surface opposing the first major surface, a drift layer of the first conductivity type formed on the first major surface of the semiconductor substrate, a buried diffusion layer of a second conductivity type formed to reach a portion near the semiconductor substrate from a surface of the drift layer, a well layer of the second conductivity type formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in a surface of the well layer between the buried diffusion layers, a trench formed to reach an inside of the drift layer from a surface of the source layer through the well layer and become shallower than the buried diffusion layer, a control electrode formed in the trench through an insulating film, a first main electrode formed on the second major surface of the semiconductor substrate, and a second main electrode connected to the source layer and the well layer.
  • FIG. 1 is a plan view showing a semiconductor element according to the first embodiment of the present invention
  • FIG. 2 is a sectional view taken along a line II—II of the semiconductor element in FIG. 1;
  • FIG. 3 is a sectional view taken along a line III—III of the semiconductor element in FIG. 1;
  • FIG. 4 is a perspective view showing the semiconductor element according to the first embodiment of the present invention.
  • FIGS. 5, 6 , 7 , 8 , 9 , 10 , 11 , 12 , and 13 are sectional views showing the steps in manufacturing the semiconductor element according to the first embodiment of the present invention.
  • FIG. 14A is a sectional view showing a semiconductor element according to the first embodiment of the present invention.
  • FIGS. 14B and 14C are views showing the relationship between the voltage and the drift layer between trenches
  • FIG. 15A is a sectional view showing a semiconductor element according to the first embodiment of the present invention.
  • FIG. 15B is a view showing the first impurity concentration distribution of the drift layer in the first embodiment
  • FIGS. 16A, 16 B, and 16 C are views showing other examples of the first impurity concentration distribution of the drift layer in the first embodiment
  • FIG. 17 is a view showing the second impurity concentration distribution of the drift layer in the first embodiment
  • FIG. 18 is a sectional view showing a semiconductor element according to the second embodiment of the present invention.
  • FIG. 19 is a sectional view showing still another semiconductor element according to the second embodiment of the present invention.
  • FIG. 20 is a sectional view showing still another semiconductor element according to the second embodiment of the present invention.
  • FIG. 21 is a sectional view showing a semiconductor element according to the third embodiment of the present invention.
  • FIG. 22 is a plan view showing circular trenches according to the fourth embodiment.
  • FIG. 23 is a sectional view and sectional view showing the circular trenches according to the fourth embodiment.
  • FIG. 24 is a plan view showing rectangular trenches according to the fourth embodiment.
  • FIG. 25 is a plan view showing hexagonal trenches according to the fourth embodiment.
  • FIG. 26 is a sectional perspective view taken along a line XXVI—XXVI of a portion having trenches in FIG. 25;
  • FIG. 27 is a perspective view showing a portion having hexagonal trenches according to the fourth embodiment.
  • FIG. 28 is a plan view showing a semiconductor element according to the fifth embodiment of the present invention.
  • FIG. 29 is a sectional perspective view taken along a line XXVIII—XXVIII of the semiconductor element in FIG. 28;
  • FIGS. 30, 31 , 32 , 33 , 34 , 35 , 36 , and 37 are perspective views showing the steps in manufacturing the semiconductor element according to the fifth embodiment of the present invention.
  • FIG. 38 is a sectional view showing the main part of a semiconductor element according to the sixth embodiment of the present invention.
  • FIG. 39 is a sectional view showing the main part of a semiconductor element according to the seventh embodiment of the present invention.
  • FIG. 40 is a sectional view showing the main part of a semiconductor element according to the eighth embodiment of the present invention.
  • FIG. 41 is a sectional view showing the main part of a semiconductor element according to the ninth embodiment of the present invention.
  • FIG. 42 is a sectional view showing the main part of a semiconductor element according to the 10th embodiment of the present invention.
  • FIG. 43 is a sectional view showing the main part of a semiconductor element according to the 11th embodiment of the present invention.
  • FIG. 44 is a sectional view showing a conventional semiconductor element.
  • the first embodiment exemplifies a buried type power MOSFET.
  • the first characteristic feature of the first embodiment will be described first.
  • the first characteristic feature is that a trench is formed in a drift layer, and a buried electrode to which a voltage independent of the voltage applied to a gate electrode is applied is formed in the trench.
  • FIG. 1 is a plan view of a semiconductor element according to the first embodiment of the present invention.
  • FIG. 2 is a sectional view taken along a line II—II of the semiconductor element in FIG. 1 .
  • FIG. 3 is a sectional view taken along a line III—III of the semiconductor element in FIG. 1 .
  • FIG. 4 is a perspective view of the semiconductor element according to the first embodiment.
  • a plurality of striped (belt-like) trenches 15 are formed in a semiconductor substrate 11 .
  • a terminal trench 15 a is formed in a terminal portion of the element.
  • an n-type drift layer 12 is formed on one surface of the n-type semiconductor substrate 11 by epitaxial growth.
  • P-type well layers 13 for MOS formation are selectively formed in the surface of the drift layer 12 .
  • N-type source layers 14 are selectively formed in the surfaces of the well layers 13 .
  • Each trench 15 is formed to reach the inside of the semiconductor substrate 11 from the surface of the source layer 14 through the well layer 13 and drift layer 12 .
  • a buried electrode 17 is formed through a first insulating film 16 in a region extending from the drift layer 12 to the semiconductor substrate 11 in this trench 15 .
  • a gate electrode 19 that is electrically insulated from the buried electrode 17 and serves as a control electrode is formed through a second insulating film 18 in a region extending from the source layer 14 to the drift layer 12 through the well layer 13 in the trench 15 .
  • a drain electrode 20 serving as a first main electrode is formed on the other surface of the semiconductor substrate 11 .
  • Source electrodes 21 that are connected to the source layers 14 and well layers 13 and serve as second main electrodes are formed on the well layers 13 .
  • the buried electrode 17 is connected to the source electrode 21 .
  • the gate electrode 19 is insulated from the buried electrode 17 and source electrode 21 by an interlevel dielectric film 22 and connected to an overlying extraction gate electrode 23 .
  • the terminal trench 15 a shown in FIG. 1 is formed in a terminal portion.
  • the voltage applied to each buried electrode 17 is controlled to optimize the tradeoff between the breakdown voltage and ON resistance of the element.
  • the buried electrode 17 is preferably connected to the source electrode 21 and fixed to the source potential, as shown in FIGS. 2 and 3. Note that the buried electrode 17 may be connected to the drain electrode 20 and fixed to the drain potential or may not be electrically connected.
  • Each trench 15 may not be formed to reach the semiconductor substrate 11 .
  • the first and second insulating films 16 and 18 may be the same insulating film such as a silicon oxide film (SiO 2 film).
  • the first and second insulating films 16 and 18 may be different insulating films.
  • the first insulating film 16 may be formed by an SiO 2 film
  • the second insulating film 18 may be formed by an SiO 2 film/Si 3 N 4 film/SiO 2 film (ONO film).
  • the first insulating film 16 is preferably thicker than the second insulating film 18 .
  • the thickness of the first insulating film 16 may be determined by a breakdown voltage, whereas the thickness of the second insulating film 18 may be determined by a threshold voltage.
  • the thickness of the first insulating film 16 is preferably larger than the value obtained by multiplying the static breakdown voltage of the element by 20 ⁇ and may be set to 3,000 ⁇ .
  • the thickness of the second insulating film 18 may be set to, for example, 400 to 450 ⁇ .
  • the drift layer 12 described above is a semiconductor layer in which depletion develops with an increase in drain voltage to mainly hold an applied voltage.
  • a method of forming a buried type power MOSFET according to the first embodiment will be described next with reference to FIGS. 5 to 13 .
  • the n-type drift layer 12 is formed on the surface of the n-type semiconductor substrate 11 by epitaxial growth.
  • the p-type well layers 13 are selectively formed in the surface of the drift layer 12 .
  • An n-type source layer (not shown) is selectively formed in the surface of the well layer 13 .
  • the trench 15 is formed to reach the inside of the semiconductor substrate 11 from the surface of the source layer through the well layer 13 and the drift layer 12 by RIE (Reactive Ion Etching).
  • the first insulating film 16 having a thickness of, for example, 3,000 ⁇ is formed on the exposed surface of the trench 15 and the surface of the well layer 13 by, for example, thermal oxidation.
  • a first polysilicon film 17 a is formed on the first insulating film 16 to fill the trench 15 .
  • the first polysilicon film 17 a is etched back, and the etched-back surface of the first polysilicon film 17 a is located below the surface of the well layer 13 . Thereafter, as shown in FIG. 10, the first insulating film 16 is etched to the etched-back surface of the first polysilicon film 17 a . Note that the first polysilicon film 17 a and first insulating film 16 may be removed at once.
  • the second insulating film 18 having a thickness of, for example, 400 to 450 ⁇ is formed on the exposed surface of the trench 15 and the surfaces of the well layers 13 and first polysilicon film 17 a by, for example, thermal oxidation. Note that the second insulating film 18 may be formed by deposition.
  • a second polysilicon film 19 a is formed on the second insulating film 18 to fill the trench 15 .
  • the second polysilicon film 19 a is etched back to expose the surface of the second insulating film 18 .
  • the buried electrode 17 and the gate electrode 19 insulated from the buried electrode 17 are formed in the trench 15 .
  • the first characteristic feature of the present invention is that the trench 15 is formed in the drift layer 12 , and the buried electrode 17 to which a voltage independent of the voltage applied to the gate electrode 19 is applied is formed in the trench 15 .
  • the drift layer 12 can be greatly depleted. Even if, therefore, the drift layer 12 is heavily doped, a high breakdown voltage can be realized. Since the energy consumed by the power MOSFET while a current flows decreases, the efficiency of the power supply can be improved.
  • Table 2 shows the relationship between the width of the drift layer 12 and the maximum impurity concentration. As indicated by Table 2, the maximum impurity concentration of the drift layer 12 is determined by the width of the drift layer 12 between the trenches 15 . Note that the maximum impurity concentration of the drift layer 12 is the impurity concentration of a portion where depletion has developed at the maximum breakdown voltage of the element.
  • the maximum impurity concentration of the drift layer 12 can be increased by decreasing the width of the drift layer 12 between thetrenches 15 . This makes it possible to further reduce the ON resistance.
  • the second characteristic feature of the first embodiment will be described next.
  • the second characteristic feature is that the voltage held by only a semiconductor layer in the prior art is shared by the first insulating layer on the surface of the electrode buried in each trench.
  • FIGS. 14B and 14C shows the relationship between the voltage and the drift layer between trenches.
  • the buried electrode 17 is formed in the trench 15 through the first insulating film 16 .
  • This first insulating film 16 is formed thick, as described above.
  • a voltage V in the drift layer 12 is decreased.
  • a strong electric field E is generated.
  • the voltage held by only a semiconductor layer in the prior art is shared by the first insulating film 16 on the surface of the buried electrode 17 in the trench 15 . Therefore, the voltage applied to the semiconductor layer can be greatly decreased as compared with the total drain voltage. This makes it possible to increase the breakdown voltage.
  • the strong electric field which is generated when positive charge in the drift layer 12 is canceled out by negative charge in the buried electrode 17 can be generated in the first insulating film 16 . Hence, the electric field can be suppressed relatively low in the semiconductor layer.
  • the dielectric constant of the oxide film is about 1 ⁇ 3 that of silicon, a voltage three times as high as that held by silicon can be held. As described above, if the dielectric constant of the first insulating film 16 surrounding the buried electrode 17 is set to be lower than that of the semiconductor substrate 11 , the breakdown voltage can be further increased.
  • the third characteristic feature of the first embodiment will be described next.
  • the third characteristic feature is that a drift layer has an impurity concentration distribution.
  • FIG. 15B shows the first impurity concentration distribution of the drift layer in the first embodiment.
  • the impurity concentration of the drift layer 12 increases toward the substrate 11 .
  • the potential of the drift layer 12 rises toward the substrate 11 , and the potential difference between the drift layer 12 and the buried electrode 17 increases. As a consequence, the negative charge in the buried electrode 17 increases. Therefore, the impurity concentration of the drift layer 12 can be increased toward the substrate 11 . This makes it possible to decrease the ON voltage as compared with a structure in which the impurity concentration of the drift layer 12 is uniform.
  • the impurity concentration of the drift layer 12 need not be uniformly increased toward the substrate 11 .
  • the impurity concentration of the drift layer 12 may be increased on average toward the substrate 11 .
  • the drift layer 12 in order to increase the impurity concentration of the drift layer 12 toward the substrate 11 , the drift layer 12 may be formed by epitaxial growth while the gas concentration is changed, thereby changing the impurity concentration of the drift layer 12 stepwise.
  • thermal diffusion may be performed after repetition of epitaxial growth and ion implantation to change the impurity concentration of the drift layer 12 stepwise so as to increase the impurity concentration of the drift layer 12 toward the substrate 11 .
  • the ON voltage can be decreased as compared with the structure in which the impurity concentration of the drift layer 12 is uniform.
  • the thickness of the first insulating film 16 on the surface of the buried electrode 17 may be increased toward the substrate 11 instead of changing the impurity concentration of the drift layer 12 in the above manner. In this case as well, the same effects as described above can be obtained.
  • FIG. 17 shows the second impurity concentration distribution of the drift layer in the first embodiment.
  • a heavily doped region 12 a in which the impurity concentration of the drift layer 12 is high is formed near a side wall of the trench 15 .
  • This heavily doped region 12 a is formed by obliquely implanting ions into a portion near a side wall of the trench 15 after the trench 15 is formed.
  • the effects of the present invention can be expected by setting the impurity concentration of the drift layer 12 to a predetermined value, the effects can be enhanced by forming the heavily doped region 12 a near a side wall of the trench 15 .
  • the maximum impurity concentration of the drift layer 12 can be increased.
  • the ON resistance can be further decreased.
  • the impurity concentration at the center line of the drift layer 12 is lower than the average impurity concentration of the drift layer 12 .
  • a great effect can be obtained, in particular, by forming the heavily doped region 12 a in only a thin portion of the surface of the side wall of the trench 15 .
  • the ON voltage and ON resistance can be further decreased as compared with the structure in which the impurity concentration of the drift layer 12 is uniform.
  • the ON resistance can be decreased, and the breakdown voltage can be increased. IN addition, a decrease in ON voltage can also be attained.
  • the buried electrode 17 may be connected to the gate electrode 19 .
  • improvements in ON resistance and breakdown voltage can be expected more than in the above embodiment.
  • the buried electrode 17 also serves as a MOS gate, and an electron storage layer is formed at the interface between the drift layer 12 and the trench 15 to promote conduction of electrons.
  • fixing the buried electrode 17 to the high voltage of the gate or a higher voltage can prevent the feedback capacitance of the gate from increasing and prevent the switching speed from decreasing.
  • the n-type drift layer 12 may be a p-type layer.
  • the impurity concentration of the n-type heavily doped region 12 a can be increased. Hence, the ON resistance can be further decreased.
  • the first and third characteristic features of the first embodiment are applied to a planar type power MOSFET.
  • a description of structures common to the first embodiment will be omitted, and only different structures will be described.
  • FIG. 18 is a sectional view of a semiconductor element according to the second embodiment of the present invention.
  • an n-type drift layer 12 is formed on one surface of an n-type semiconductor substrate 11 by epitaxial growth.
  • P-type well layer 13 for MOS formation are selectively formed in the surface of the drift layer 12 .
  • N-type source layers 14 are selectively formed in the surfaces of the well layers 13 .
  • Trenches 15 are formed to reach the inside of the semiconductor substrate 11 from the surface of the drift layer 12 through the drift layer 12 .
  • a buried electrode 17 is formed in each trench 15 through a first insulating film 16 .
  • a gate electrode 19 serving as a control gate is formed on the drift layer 12 through a gate insulating film 24 .
  • a drain electrode 20 serving as a first main electrode is formed on the other surface of the semiconductor substrate 11 .
  • a source electrode 21 serving as a second main electrode which is insulated from the gate electrode 19 and connected to the source layer 14 and well layer 13 is formed on the well layer 13 .
  • the first insulating film 16 is formed relatively thick and made of, for example, an SiO 2 film as in the first embodiment.
  • the buried electrode 17 may be connected to the drain electrode 20 or source electrode 21 or may not be connected thereto.
  • the trench 15 may not be formed to reach the semiconductor substrate 11 .
  • a planar type MOSFET has no gate electrode 19 formed in the trench 15 , and hence facilitates the manufacturing process.
  • planar type power MOSFET having the following structure can obtain the same effects as those of the power MOSFET shown in FIG. 18 .
  • the well layers 13 and source layers 14 may be formed on two upper ends of the trench 15 , and the source electrode 21 may be formed on the trench 15 .
  • a reduction in size can be attained as compared with the power MOSFET shown in FIG. 18 .
  • the well layer 13 and source layer 14 may be formed on one upper end of the trench 15 , and the source electrode 21 may be formed on the trench 15 .
  • the distance between the trenches 15 can be decreased.
  • the impurity concentration of the drift layer 12 can therefore be increased as compared with the power MOSFET shown in FIG. 18 . This makes it possible to further decrease the ON resistance.
  • a reduction in size can be attained as compared with the power MOSFET shown in FIG. 18 .
  • the first to third characteristic features of the first embodiment are applied to a Schottky barrier diode.
  • a description of structures common to the first embodiment will be omitted, and only different structures will be described.
  • FIG. 21 is a sectional view of a semiconductor element according to the third embodiment.
  • an n-type drift layer 12 is formed on one surface of an n-type semiconductor substrate 11 by epitaxial growth. Trenches 15 are formed to reach the inside of the semiconductor substrate 11 from the surface of the drift layer 12 through the drift layer 12 .
  • a buried electrode 17 is formed in each trench 15 through a first insulating film 16 .
  • An anode electrode 31 serving as a first main electrode is formed on the other surface of the semiconductor substrate 11 .
  • Cathode electrodes 32 serving as second main electrodes are formed on the drift layer 12 .
  • the first insulating film 16 is formed relatively thick and made of, for example, an SiO 2 film as in the first embodiment.
  • the buried electrode 17 may be connected to the anode electrode 31 or cathode electrode 32 or may not be electrically connected thereto.
  • Each trench 15 may not be formed to reach the semiconductor substrate 11 .
  • the same effects as those of the first embodiment can be obtained.
  • a Schottky barrier diode in a switching power supply, synchronous rectification by the MOSFET can be replaced with a diode having a simple structure.
  • IGBT Insulated Gate Bipolar Transistor
  • SIT Static Induction Transistor
  • each trench in the first to third embodiments may have a striped pattern like the one described above or may have the following shape.
  • FIG. 22 is a plan view of a structure having circular trenches according to the fourth embodiment.
  • FIG. 23 is a partially cutaway plan view of a terminal portion having trenches according to the fourth embodiment.
  • FIG. 22 schematically shows only trenches at the planar position.
  • a plurality of circular trenches 41 are formed in a semiconductor substrate 11 at the vertices of a regular triangle.
  • a guard ring structure is applied to the present invention, and an n-type diffusion layer 42 is formed at a terminal portion of this structure.
  • buried gates 17 in the terminal portion may be electrically connected to buried gates 17 in an element region 11 a or set in a floating state.
  • the circular trenches 41 according to the fourth embodiment allow the structure to have high isotropy and maintain planar uniformity. This makes it difficult to unbalance an electric field in the planar direction, and reduces the possibility of breakdown due to a strong electric field.
  • This structure is obtained by forming holes in the semiconductor substrate (silicon substrate) 11 . As compared with the structure obtained by forming trenches 15 in a striped pattern, therefore, this structure can prevent troubles, e.g., collapse of silicon columns in forming the trenches 15 .
  • rectangular trenches 43 may be formed.
  • planar uniformity can be maintained by forming rectangular trenches 43 in the semiconductor substrate 11 at the vertices of squares. With this structure, the same effects as those obtained by the circular trenches 41 described above can be obtained.
  • FIG. 25 is a plan view of a structure having hexagonal trenches according to the fourth embodiment.
  • FIG. 26 is a sectional perspective view taken along a line XXVI—XXVI of the trench structure in FIG. 25 .
  • FIG. 27 is a sectional perspective view of a portion having hexagonal trenches. For the sake of simplicity, FIG. 25 schematically shows only trenches at the planar position.
  • a plurality of hexagonal trenches having a tortoise-shaped pattern are formed in the semiconductor substrate 11 .
  • the buried electrode 17 in each trench 44 is connected to a source electrode 21 .
  • the trenches 44 surround element portions such as p-type well layers 13 and n-type source layers 14 . At a terminal portion of this structure, therefore, the trenches 44 are naturally terminated. Note that the potential of each buried electrode 17 at the terminal portion is preferably set to be equal to that of each buried electrode 17 in the element region.
  • the fifth embodiment exemplifies a buried type power MOSFET.
  • This embodiment differs from the first embodiment in the first characteristic feature but has the same characteristic features as the second and third characteristic features. More specifically, in the first embodiment, a gate electrode and a buried electrode to which a voltage independent of the voltage applied to the gate electrode is applied are formed in the same trench formed in the drift layer. In contrast to this, in this embodiment, the gate electrode and buried electrode are formed in different trenches.
  • a detailed description of structures common to the first embodiment will be omitted.
  • FIG. 28 is a plan view of a semiconductor element according to the fifth embodiment of the present invention. Illustrations of source electrodes, insulating films, and the like are omitted from FIG. 28 .
  • FIG. 29 is a sectional perspective view taken along a line XXVIII—XXVIII of the semiconductor element in FIG. 28 .
  • an n-type drift layer 12 is formed on one surface of an n + -type semiconductor substrate 11 .
  • P-type wells 13 are formed in the surface of the drift layer 12 .
  • Striped n + -type source layers 14 are selectively formed in the surfaces of the well layers 13 in the horizontal direction (lateral direction on the drawing).
  • a plurality of striped first trenches 51 are formed in the vertical direction (up-and-down direction on the drawing) to reach a portion in the drift layer 12 which is located near the semiconductor substrate 11 from the surfaces of the source layers 14 through the well layers 13 .
  • a buried electrode 53 is formed in each first insulating film 51 through a first insulating film 52 for holding a breakdown voltage.
  • a plurality of striped second trenches 61 are formed to reach the inside of the drift layer 12 from the surfaces of the source layers 14 through the well layers 13 so as to cross the first trenches 51 , for example, at right angles.
  • the second trench 61 is preferably formed to be shallower than the first trench 51 .
  • a gate electrode 63 serving as a control electrode is formed through a second insulating film 62 for forming a channel.
  • a drain electrode 20 is formed on the other surface of the semiconductor substrate 11 .
  • Source electrodes 21 connected to the source layers 14 and well layers 13 are formed on the well layers 13 .
  • the buried electrode 53 is connected to the source electrode 21 .
  • the gate electrode 63 is insulated from the buried electrode 53 and source electrode 21 through an interlevel dielectric film, and is connected to an extraction gate electrode (not shown) on the upper layer.
  • the voltage applied to each buried electrode 53 is controlled to optimize the tradeoff between the breakdown voltage and ON resistance of the element.
  • the first and second insulating films 52 and 62 may be the same insulating film such as a silicon oxide film (SiO 2 film).
  • the first and second insulating films 52 and 62 may be different insulating films.
  • the first insulating film 52 may be formed by an SiO 2 film
  • the second insulating film 62 may be formed by an SiO 2 film/Si 3 N 4 film/ONO film.
  • the first insulating film 52 is preferably thicker than the second insulating film 62 .
  • the thickness of the first insulating film 52 may be determined by a breakdown voltage, whereas the thickness of the second insulating film 62 may be determined by a threshold voltage.
  • the impurity concentration of the drift layer 12 is preferably increased toward the semiconductor substrate 11 .
  • a method of forming a buried type power MOSFET according to the fifth embodiment will be described next with reference to FIGS. 30 to 37 .
  • the n-type drift layer 12 is formed on the surface of the n + -type semiconductor substrate 11 by epitaxial growth.
  • the p-type well layer 13 is formed in the surface of the drift layer 12 .
  • the striped n + -type source layers 14 are selectively formed in the surface of the well layer 13 at predetermined intervals in the horizontal direction.
  • the plurality of striped first trenches 51 are vertically formed across the source layers 14 by, for example, RIE.
  • the first trenches 51 are formed to reach a portion in the drift layer 12 which is located near the semiconductor substrate 11 from the surface of the well layer 13 through the well layer 13 .
  • the first insulating film 52 having a thickness of, for example, 3,000 ⁇ to 30,000 ⁇ is formed on the inner surface and bottom surface of each first trench 51 by, for example, thermal oxidation.
  • a polysilicon film is formed in the first trench 51 and on the well layer 13 to fill the first trench 51 .
  • This polysilicon film is etched back such that the etched-back surface becomes flush with the surface of the well layer 13 .
  • the first insulating film 52 is formed on the surface of the polysilicon film on the upper portion of the first trench 51 by, for example, thermal oxidation. Note that the first insulating film 52 on the upper portion of the first trench 51 may be formed by deposition. As a result, the buried electrode 53 made of polysilicon is formed in the first trench 51 .
  • the plurality of second trenches 61 are formed between the first trenches 51 in a direction to cross the first trenches 51 (a direction perpendicular to the first trenches 51 ), i.e., the horizontal direction by, for example, RIE.
  • the source layers 14 may not be formed in a striped pattern as shown in FIG. 31, but the source layer 14 may be formed on the entire surface of the well layer 13 and formed into the pattern shown in FIG. 35 by forming the second trenches 61 .
  • This second trench 61 is formed to reach the inside of the drift layer 12 from the surface of the source layer 14 through the well layer 13 , but is shallower than the first trench 51 .
  • This second trench 61 need not always be formed in contact with the first trench 51 .
  • the second insulating film 62 having a thickness of, for example, 400 to 450 ⁇ is formed on the side and bottom surfaces of the second trench 61 by, for example, thermal oxidation.
  • a polysilicon film is formed in the second trench 61 and on the well layer 13 to fill the second trench 61 .
  • This polysilicon film is then etched back such that the etched-back surface becomes flush with the surface of the well layer 13 .
  • the second insulating film 62 is formed on the surface of the polysilicon film on the upper portion of the second trench 61 by, for example, thermal oxidation. Note that the second insulating film 62 on the upper portion of the second trench 61 may be formed by deposition. As a result, the gate electrode 63 made of polysilicon is formed in the second trench 61 .
  • the same effects as those of the first embodiment can be obtained.
  • the buried electrode 53 and gate electrode 63 are respectively formed in the different trenches 51 and 61 , the manufacturing process is facilitated as compared with the first embodiment in which these electrodes are formed in the same trench 15 .
  • the gate structure with shallow trenches (or a planar structure to be described later) is formed after the deep trenches are formed.
  • deep trenches may be formed and filled after a gate structure is formed, for example, immediately before the electrode formation step.
  • the second trenches 61 are formed to cross the first trenches 51 .
  • the second trenches 61 may be formed along the first trenches 51 , and the source layers 14 may be formed in contact with the second trenches 61 .
  • the source layers 14 between the gate electrodes 63 are formed such that one end portion of each source layer 14 is connected to the corresponding gate electrode 63 , and the other end portion of each source layer 14 does not come into contact with the other end portion of an adjacent source layer 14 .
  • the other end portion of each source layer 14 may come into contact with the other end portion of an adjacent source layer 14 .
  • the source layer 14 may be formed on the entire surface of the well layer 13 and formed into the pattern shown in FIG. 35 by self alignment using the second trenches 61 .
  • the first trenches 51 and second trenches 61 are formed in striped patterns and cross at right angles.
  • the first trenches 51 for ensuring a breakdown voltage are formed independently of the second trenches 61 for the formation of gates.
  • these trenches may be circular, rectangular, hexagonal, or the like instead of being striped, as described above.
  • these trenches may take any pattern, e.g., extending parallel or crossing at 60°, instead of crossing at right angles.
  • the first trenches 51 may be formed to reach the semiconductor substrate 11 .
  • FIG. 38 is a sectional view showing the main part of a power MOSFET (semiconductor element) according to the sixth embodiment of the present invention.
  • This embodiment is the same as the fifth embodiment except in the structure of a buried gate electrode. A detailed description of structures common to the fifth embodiment will be omitted.
  • an insulating film 55 made of SiO 2 or the like is formed on the inner surface of a second trench 51 except for the bottom surface.
  • the trench 51 is the filled with a semi-insulating film 56 such as an SIPOS (Semi-Insulating Polycrystalline Silicon) film, thereby forming a buried electrode having the same function as that of the buried electrode in the sixth embodiment.
  • SIPOS Semi-Insulating Polycrystalline Silicon
  • This sixth embodiment described above can obtain the same effects as those of the fifth embodiment.
  • FIG. 39 is a sectional view showing the main part of a power MOSFET (semiconductor element) according to the seventh embodiment of the present invention.
  • This embodiment is the same as the fifth embodiment except for the structure of each gate electrode. A detailed description of structures common to the fifth embodiment will be omitted.
  • this embodiment uses gate electrodes having a planar structure. Gate insulating films 622 are formed in place of the second insulating films 62 in the fifth embodiment, and gate electrodes 633 are formed in place of the gate electrodes 63 .
  • striped p-type well layers 13 are selectively formed in the surface of a drift layer 12 in the horizontal direction.
  • Striped n + -type source layers 14 are selectively formed in the surfaces of the well layers 13 .
  • Striped first trenches 51 are then formed in the vertical direction to cross the striped well layers 13 and source layers 14 at right angles.
  • a buried electrode 53 is formed in each first trench 51 through a first insulating film 52 .
  • the gate electrode 633 is formed on the surfaces of the well layer 13 and drift layer 12 between one of adjacent source layers 14 and the other source layer 14 through the gate insulating film (second insulating film) 622 .
  • the well layers 13 and source layers 14 are formed to cross the trenches 51 . However, they may be formed along the trenches 51 .
  • the trenches 51 and gate electrodes 633 are formed in the striped pattern and cross each other.
  • the first trenches 51 for ensuring a breakdown voltage are formed independently of the gate electrodes 633 .
  • these trenches may be circular, rectangular, hexagonal, or the like instead of being striped, as described above.
  • these trenches may take any pattern, e.g., extending parallel or crossing at 60°, instead of crossing at right angles.
  • the trenches 51 may be formed to reach the semiconductor substrate 11 .
  • FIG. 40 is a perspective view showing the main part of a power MOSFET according to the eighth embodiment of the present invention.
  • This embodiment is the same as the fifth embodiment except for the structure of each buried gate electrode. A description of structures common to the fifth embodiment will be omitted, and only different structures will be described.
  • an n-type drift layer 12 is formed on one surface of an n + -type semiconductor substrate 11 , and a p-type well layer 13 is formed in the surface of the drift layer 12 .
  • a plurality of p-type buried diffusion layers 70 serving as striped buried electrodes are formed through the well layer 13 in the vertical direction (up-and-down direction on the drawing) to reach a portion in the drift layer 12 which is located near the semiconductor substrate 11 from the surfaces of source layers 14 .
  • n + -type source layers 14 are selectively formed in the well layer 13 at predetermined intervals in a direction to cross the buried diffusion layers 70 (e.g., a direction to cross them at right angles), i.e., the horizontal direction.
  • a plurality of striped second trenches 61 are formed to reach the inside of the drift layer 12 from the surface of the source layers 14 through the well layer 13 so as to cross the buried diffusion layers 70 , for example, at right angles.
  • the second trenches 61 are preferably formed to be shallower than the buried diffusion layers 70 .
  • a gate electrode 63 serving as a control electrode is formed in each second trench 61 through a second insulating film 62 for channel formation.
  • the gate electrodes 63 and source layers 14 are irrelevant to the operation of the MOSFET. Hence, no problem arises.
  • the gate electrodes 63 and source layers 14 be selectively formed only in the regions between the buried diffusion layers 70 . In this case, however, the manufacturing process is slightly complicated.
  • a drain electrode 20 is formed on the other surface of the semiconductor substrate 11 , and source electrodes 21 connected to the source layers 14 and well layer 13 are formed on the well layer 13 .
  • the buried diffusion layers 70 are connected to the source electrodes 21 .
  • the gate electrodes 63 are insulated from the buried diffusion layers 70 and source electrodes 21 and connected to overlying extraction gate electrodes (not shown).
  • FIG. 41 is a sectional view showing the main part of a power MOSFET (semiconductor element) according to the ninth embodiment of the present invention.
  • This embodiment is the same as the eighth embodiment except for the structure of each buried diffusion layer. A description of structures common to the eighth embodiment will be omitted, and only different structures will be described.
  • a first trench 51 is formed, and a p-type impurity is implanted into the inner surface of the first trench 51 by, for example, oblique implantation. Thereafter, re-diffusion is performed to form a p-type buried diffusion layer 70 serving as a buried electrode.
  • an insulating film 72 such as an SiO 2 film is buried in this first trench 51 .
  • FIG. 42 is a sectional view showing the main part of a power MOSFET (semiconductor element) according to the 10th embodiment of the present invention.
  • This embodiment is the same as the eighth embodiment except for the structure of each buried diffusion layer. A description of structures common to the eighth embodiment will be omitted, and only different structures will be described.
  • a first trench 51 is formed, and p- and n-type impurities are implanted into the inner surface of the first trench 51 by, for example, oblique implantation. Thereafter, re-diffusion is performed to form an n-type diffusion layer 72 on the trench 51 side and also form a p-type buried diffusion layer 70 serving as a buried electrode between the n-type diffusion layer 72 and a drift layer 12 .
  • This first trench 51 is further filled with an insulating film 71 such as an SiO 2 film.
  • a structural feature of each of the fifth to 10th embodiments of the present invention described above is that channel regions are formed independently of deep trench regions for ensuring a breakdown voltage. That is, a characteristic feature of these embodiments is that channel structures (trench structures and planar structures in the embodiments) are formed in other regions independently of the material used to fill the deep trench regions and trench structure.
  • FIG. 43 is a sectional view showing the main part of a power MOSFET (semiconductor element) according to the 11th embodiment of the present invention.
  • an n-type drift layer 12 is formed on one surface of an n + -type semiconductor substrate 11 .
  • a plurality of p-type buried diffusion layers 80 serving as striped buried electrodes are formed at predetermined intervals in the vertical direction to reach a portion near the semiconductor substrate 11 from the surface of the drift layer 12 .
  • a p-type well layer 13 is formed in the surface of the drift layer 12 including these buried diffusion layers 80 .
  • Striped n + -type source layers 14 are selectively formed in portions of the well layer 13 which are located between the buried diffusion layers 80 along the buried diffusion layers 80 .
  • Striped second trenches 61 are formed through the well layer 13 along the buried diffusion layers 80 to reach the inside of the drift layer 12 from the surfaces of the source layers 14 .
  • the second trenches 61 are preferably formed to be shallower than the buried diffusion layers 80 .
  • a gate electrode 63 serving as a control electrode is formed in each second trench 61 through a second insulating film 62 for channel formation.
  • a drain electrode 20 is formed on the other surface of the semiconductor substrate 11 .
  • Source electrodes 21 connected to the well layer 13 and source layers 14 are formed on the well layer 13 .
  • the buried diffusion layers 80 are connected to the source electrodes 21 through the well layer 13 .
  • the gate electrodes 63 are insulated from the buried diffusion layers 80 and source electrodes 21 and connected to overlying extraction gate electrodes (not shown).
  • the same effects as those of the fifth embodiment can be obtained.
  • the gate electrodes 63 , source layers 14 , and buried diffusion layers 80 are formed in the same direction. This structure facilitates the manufacturing process as compared with each embodiment in which these components cross each other.
  • the ON resistance can be decreased, and the breakdown voltage can be increased.
  • a decrease in ON voltage and a reduction in element size can be attained.
  • the present invention According to the structure of the present invention, no buried diffusion layer as in the prior art needs to be formed to attain a decrease in ON resistance. Obviously, this makes it possible to prevent a decrease in switching speed and a deterioration in the characteristics of a reverse-conducting diode. In addition, the present invention can achieve a reduction in cost as compared with a structure having buried diffusion layers.

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Cited By (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040155287A1 (en) * 2000-06-30 2004-08-12 Ichiro Omura Power semiconductor switching element
US20050006699A1 (en) * 2003-05-13 2005-01-13 Kabushiki Kaisha Toshiba Semiconductor device and its manufacturing method
US20050167749A1 (en) * 2001-09-07 2005-08-04 Power Integrations, Inc. High-voltage vertical transistor with edge termination structure
US20050253190A1 (en) * 2004-04-09 2005-11-17 Kabushiki Kaisha Toshiba Semiconductor device
US20060214197A1 (en) * 2005-02-22 2006-09-28 Kabushiki Kaisha Toshiba Semiconductor device
US20060273386A1 (en) * 2005-05-26 2006-12-07 Hamza Yilmaz Trench-gate field effect transistors and methods of forming the same
US20070007537A1 (en) * 2005-07-04 2007-01-11 Kabushiki Kaisha Toshiba Semiconductor device
WO2006108011A3 (fr) * 2005-04-06 2007-04-05 Fairchild Semiconductor Transistors a effet de champ a grille en tranchees, et procedes de creation desdits transistors
US20070108515A1 (en) * 2003-11-29 2007-05-17 Koninklijke Philips Electronics, N.V. Trench mosfet
US20070114511A1 (en) * 2003-07-03 2007-05-24 Epivalley Co., Ltd. lll-Nitride compound semiconductor light emiting device
US7319256B1 (en) 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
US20080017920A1 (en) * 2006-01-05 2008-01-24 Steven Sapp Structure and method for improving shielded gate field effect transistors
US7345342B2 (en) 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7352036B2 (en) 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
US20080135930A1 (en) * 2006-11-14 2008-06-12 Kabushiki Kaisha Toshiba Power semiconductor device
US20080173876A1 (en) * 2007-01-18 2008-07-24 Fuji Electric Device Technology Co., Ltd. Insulated gate silicon carbide semiconductor device
US20080197361A1 (en) * 2007-01-29 2008-08-21 Fuji Electric Device Technology Co., Ltd. Insulated gate silicon carbide semiconductor device and method for manufacturing the same
US7429523B2 (en) 2001-10-17 2008-09-30 Fairchild Semiconductor Corporation Method of forming schottky diode with charge balance structure
US7446374B2 (en) 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US20090008706A1 (en) * 2003-05-20 2009-01-08 Yedinak Joseph A Power Semiconductor Devices with Shield and Gate Contacts and Methods of Manufacture
US20090051000A1 (en) * 2007-08-21 2009-02-26 Jeng Gong Semiconductor device structure
US7514322B2 (en) 2005-06-10 2009-04-07 Fairchild Semiconductor Corporation Shielded gate field effect transistor
US20090111231A1 (en) * 2005-06-29 2009-04-30 Grebs Thomas E Method for Forming Shielded Gate Field Effect Transistor Using Spacers
US7582519B2 (en) 2002-11-05 2009-09-01 Fairchild Semiconductor Corporation Method of forming a trench structure having one or more diodes embedded therein adjacent a PN junction
US20100013008A1 (en) * 2008-03-12 2010-01-21 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US20100123187A1 (en) * 2008-11-14 2010-05-20 Burke Peter A Contact structure for semiconductor device having trench shield electrode and method
US20100123188A1 (en) * 2008-11-14 2010-05-20 Prasad Venkatraman Semiconductor device having trench shield electrode structure
US20100140689A1 (en) * 2008-12-08 2010-06-10 Yedinak Joseph A Trench-Based Power Semiconductor Devices with Increased Breakdown Voltage Characteristics
US20100140695A1 (en) * 2008-12-08 2010-06-10 Yedinak Joseph A Trench-Based Power Semiconductor Devices With Increased Breakdown Voltage Characteristics
US20100163950A1 (en) * 2008-06-30 2010-07-01 Jon Gladish Power Device with Monolithically Integrated RC Snubber
US20100200910A1 (en) * 2009-02-09 2010-08-12 Joseph Yedinak Semiconductor Devices with Stable and Controlled Avalanche Characteristics and Methods of Fabricating the Same
US20100207205A1 (en) * 2009-02-19 2010-08-19 Grebs Thomas E Structures and Methods for Improving Trench-Shielded Semiconductor Devices and Schottky Barrier Rectifier Devices
US20100314707A1 (en) * 2009-06-12 2010-12-16 Yedinak Joseph A Reduced Process Sensitivity of Electrode-Semiconductor Rectifiers
US20100320534A1 (en) * 2008-06-20 2010-12-23 James Pan Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices
US20100327359A1 (en) * 2005-05-20 2010-12-30 Yoshito Nakazawa Semiconductor device and manufacturing method of the same
US20110018059A1 (en) * 2009-07-24 2011-01-27 Dixie Dunn Shield Contacts in a Shielded Gate MOSFET
US20110049615A1 (en) * 2009-08-25 2011-03-03 Kabushiki Kaisha Toshiba Power semiconductor device
CN102403315A (zh) * 2010-09-07 2012-04-04 株式会社东芝 半导体装置
US20120292693A1 (en) * 2009-08-31 2012-11-22 Alpha & Omega Semiconductor Incorporated Fabrication of trench dmos device having thick bottom shielding oxide
US8319290B2 (en) 2010-06-18 2012-11-27 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
US8552535B2 (en) 2008-11-14 2013-10-08 Semiconductor Components Industries, Llc Trench shielding structure for semiconductor device and method
US20130334596A1 (en) * 2012-06-15 2013-12-19 Magnachip Semiconductor, Ltd. Semiconductor device and fabricating method thereof
CN103681851A (zh) * 2012-09-12 2014-03-26 株式会社东芝 电力半导体元件
US8698234B2 (en) * 2006-12-01 2014-04-15 Infineon Technologies Austria Ag Electronic device with connecting structure
US8829641B2 (en) 2001-01-30 2014-09-09 Fairchild Semiconductor Corporation Method of forming a dual-trench field effect transistor
US20140332845A1 (en) * 2010-10-31 2014-11-13 Madhur Bobde Topside structures for an insulated gate bipolar transistor (igbt) device to achieve improved device perforemances
US8921184B2 (en) 2012-05-14 2014-12-30 Semiconductor Components Industries, Llc Method of making an electrode contact structure and structure therefor
US8928077B2 (en) 2007-09-21 2015-01-06 Fairchild Semiconductor Corporation Superjunction structures for power devices
US20150028382A1 (en) * 2012-04-25 2015-01-29 Abb Schweiz Ag Insulated gate bipolar transistor with high emitter gate capacitance
CN104380471A (zh) * 2012-06-13 2015-02-25 株式会社电装 碳化硅半导体装置及其制造方法
US9029215B2 (en) 2012-05-14 2015-05-12 Semiconductor Components Industries, Llc Method of making an insulated gate semiconductor device having a shield electrode structure
US9076838B2 (en) 2013-09-13 2015-07-07 Infineon Technologies Ag Insulated gate bipolar transistor with mesa sections between cell trench structures and method of manufacturing
US9105679B2 (en) 2013-11-27 2015-08-11 Infineon Technologies Ag Semiconductor device and insulated gate bipolar transistor with barrier regions
DE102014119395A1 (de) * 2014-12-22 2016-06-23 Infineon Technologies Ag Transistorbauelement mit Feldelektrode
US20160181372A1 (en) * 2013-07-26 2016-06-23 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing same
US9385228B2 (en) 2013-11-27 2016-07-05 Infineon Technologies Ag Semiconductor device with cell trench structures and contacts and method of manufacturing a semiconductor device
DE102015100390A1 (de) * 2015-01-13 2016-07-14 Infineon Technologies Austria Ag Halbleitervorrichtung mit feldplattenstrukturen und gateelektrodenstrukturen zwischen den feldplattenstrukturen sowie herstellungsverfahren
CN105957884A (zh) * 2016-06-24 2016-09-21 上海格瑞宝电子有限公司 一种分栅栅极沟槽结构和沟槽肖特基二极管及其制备方法
US9496391B2 (en) 2013-03-15 2016-11-15 Fairchild Semiconductor Corporation Termination region of a semiconductor device
US9553179B2 (en) 2014-01-31 2017-01-24 Infineon Technologies Ag Semiconductor device and insulated gate bipolar transistor with barrier structure
US9666663B2 (en) 2013-08-09 2017-05-30 Infineon Technologies Ag Semiconductor device with cell trench structures and contacts and method of manufacturing a semiconductor device
US9818743B2 (en) 2013-06-21 2017-11-14 Infineon Technologies Americas Corp. Power semiconductor device with contiguous gate trenches and offset source trenches
USRE46799E1 (en) * 2002-09-25 2018-04-17 Kabushiki Kaisha Toshiba Semiconductor device with alternating conductivity type layers having different vertical impurity concentration profiles
US10249721B2 (en) 2013-04-04 2019-04-02 Infineon Technologies Austria Ag Semiconductor device including a gate trench and a source trench
US20190393314A1 (en) * 2013-12-13 2019-12-26 Power Integrations, Inc. Vertical Transistor Device Structure with Cylindrical-Shaped Field Plates
CN112786695A (zh) * 2019-11-08 2021-05-11 株洲中车时代电气股份有限公司 一种分裂栅沟槽功率半导体器件
US20210249535A1 (en) * 2020-02-07 2021-08-12 Rohm Co., Ltd. Semiconductor device
US12080792B2 (en) 2019-04-23 2024-09-03 Denso Corporation Semiconductor device and method for manufacturing same
US12356694B2 (en) 2022-03-23 2025-07-08 Kabushiki Kaisha Toshiba Semiconductor device
US12426341B2 (en) * 2021-03-01 2025-09-23 Wolfspeed, Inc. Semiconductor devices having gate resistors with low variation in resistance values

Families Citing this family (197)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6870220B2 (en) * 2002-08-23 2005-03-22 Fairchild Semiconductor Corporation Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses
US6911694B2 (en) * 2001-06-27 2005-06-28 Ricoh Company, Ltd. Semiconductor device and method for fabricating such device
US6635544B2 (en) 2001-09-07 2003-10-21 Power Intergrations, Inc. Method of fabricating a high-voltage transistor with a multi-layered extended drain structure
US7221011B2 (en) * 2001-09-07 2007-05-22 Power Integrations, Inc. High-voltage vertical transistor with a multi-gradient drain doping profile
DE10207309B4 (de) * 2002-02-21 2015-07-23 Infineon Technologies Ag MOS-Transistoreinrichtung
CN100437942C (zh) * 2002-05-31 2008-11-26 Nxp股份有限公司 沟槽栅半导体器件及制造方法
CN100514672C (zh) * 2002-08-23 2009-07-15 快捷半导体有限公司 用于改进mos栅控从而降低米勒电容和开关损失的方法和装置
US8080459B2 (en) * 2002-09-24 2011-12-20 Vishay-Siliconix Self aligned contact in a semiconductor device and method of fabricating the same
JP4202149B2 (ja) * 2003-01-28 2008-12-24 ローム株式会社 半導体装置およびその製造方法
JP4166102B2 (ja) * 2003-02-26 2008-10-15 トヨタ自動車株式会社 高耐圧電界効果型半導体装置
DE10313712B4 (de) 2003-03-27 2008-04-03 Infineon Technologies Ag Laterales mittels Feldeffekt steuerbares Halbleiterbauelement für HF-Anwendungen
WO2004102670A2 (fr) * 2003-05-13 2004-11-25 Koninklijke Philips Electronics N.V. Dispositifs a semi-conducteurs pourvus d'une zone de formation de champ
DE10324754B4 (de) 2003-05-30 2018-11-08 Infineon Technologies Ag Halbleiterbauelement
DE10341793B4 (de) 2003-09-10 2021-09-23 Infineon Technologies Ag Halbleiterbauelement und Verfahren zu dessen Herstellung
DE10355588B4 (de) * 2003-11-28 2006-06-14 Infineon Technologies Ag MOS-Transistoreinrichtung
GB0327792D0 (en) * 2003-11-29 2003-12-31 Koninkl Philips Electronics Nv Trench insulated gate field effect transistor
JP4699692B2 (ja) 2003-12-26 2011-06-15 ローム株式会社 半導体装置の製造方法および半導体装置
JP2005197287A (ja) 2003-12-26 2005-07-21 Rohm Co Ltd 半導体装置およびその製造方法
JP4903055B2 (ja) * 2003-12-30 2012-03-21 フェアチャイルド・セミコンダクター・コーポレーション パワー半導体デバイスおよびその製造方法
DE10361715B4 (de) 2003-12-30 2010-07-29 Infineon Technologies Ag Verfahren zur Erzeugung eines Übergangsbereichs zwischen einem Trench und einem den Trench umgebenden Halbleitergebiet
JP4564362B2 (ja) 2004-01-23 2010-10-20 株式会社東芝 半導体装置
US7405452B2 (en) 2004-02-02 2008-07-29 Hamza Yilmaz Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics
GB0404748D0 (en) * 2004-03-03 2004-04-07 Koninkl Philips Electronics Nv Trench field effect transistor and method of making it
US8564051B2 (en) * 2004-04-09 2013-10-22 International Rectifier Corporation Power semiconductor device with buried source electrode
DE102004021050A1 (de) * 2004-04-29 2005-11-24 Infineon Technologies Ag Feldeffekt-Halbleiterbauelement
DE102004021391B4 (de) * 2004-04-30 2008-10-02 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Halbleiterschaltungsanordnung
US7183610B2 (en) * 2004-04-30 2007-02-27 Siliconix Incorporated Super trench MOSFET including buried source electrode and method of fabricating the same
DE102004024660A1 (de) * 2004-05-18 2005-12-15 Infineon Technologies Ag Integrierte Halbleiterbauelementanordnung und Verfahren zu deren Herstellung
DE102004024885B4 (de) * 2004-05-19 2007-09-06 Infineon Technologies Ag Halbleiterbauelement und Verfahren zu dessen Herstellung
US20050269630A1 (en) * 2004-06-04 2005-12-08 Jianjun Cao Trench type semiconductor device with reduced Qgd
DE102004029435B4 (de) * 2004-06-18 2017-02-16 Infineon Technologies Ag Feldplattentrenchtransistor
DE102004036509B4 (de) * 2004-07-28 2010-09-09 Infineon Technologies Ag Verfahren zum Herstellen eines Trenchtransistors
JP5259920B2 (ja) * 2004-08-04 2013-08-07 ローム株式会社 半導体装置およびその製造方法
CN100499163C (zh) * 2004-08-04 2009-06-10 罗姆股份有限公司 半导体装置及其制造方法
DE102004041198B4 (de) * 2004-08-25 2016-06-09 Infineon Technologies Austria Ag Laterales Halbleiterbauelement mit einer Feldelektrode und einer Entladestruktur
JP4851075B2 (ja) * 2004-08-26 2012-01-11 新電元工業株式会社 半導体装置の製造方法
GB0419558D0 (en) * 2004-09-03 2004-10-06 Koninkl Philips Electronics Nv Vertical semiconductor devices and methods of manufacturing such devices
DE102004044619B4 (de) * 2004-09-13 2009-07-16 Infineon Technologies Ag Kondensatorstruktur in Grabenstrukturen von Halbleiterbauteilen und Halbleiterbauteile mit derartigen Kondensatorstrukturen und Verfahren zur Herstellung derselben
DE102004045944B4 (de) 2004-09-22 2018-08-16 Infineon Technologies Ag MOS-Feldeffekttransistor
DE102004046697B4 (de) * 2004-09-24 2020-06-10 Infineon Technologies Ag Hochspannungsfestes Halbleiterbauelement mit vertikal leitenden Halbleiterkörperbereichen und einer Grabenstruktur sowie Verfahren zur Herstellung desselben
US7135740B2 (en) 2004-09-27 2006-11-14 Teledyne Licensing, Llc High voltage FET switch with conductivity modulation
JP4913336B2 (ja) * 2004-09-28 2012-04-11 ルネサスエレクトロニクス株式会社 半導体装置
DE102004047772B4 (de) * 2004-09-30 2018-12-13 Infineon Technologies Ag Lateraler Halbleitertransistor
US7265415B2 (en) 2004-10-08 2007-09-04 Fairchild Semiconductor Corporation MOS-gated transistor with reduced miller capacitance
JP2006128506A (ja) * 2004-10-29 2006-05-18 Sharp Corp トレンチ型ｍｏｓｆｅｔ及びその製造方法
DE102004057237B4 (de) * 2004-11-26 2007-02-08 Infineon Technologies Ag Verfahren zum Herstellen von Kontaktlöchern in einem Halbleiterkörper sowie Transistor mit vertikalem Aufbau
US7598586B2 (en) 2004-12-24 2009-10-06 Rohm Co., Ltd. Semiconductor device and production method therefor
JP2006202931A (ja) 2005-01-20 2006-08-03 Renesas Technology Corp 半導体装置およびその製造方法
JP4867171B2 (ja) * 2005-01-21 2012-02-01 富士電機株式会社 半導体装置の製造方法
US7781826B2 (en) * 2006-11-16 2010-08-24 Alpha & Omega Semiconductor, Ltd. Circuit configuration and manufacturing processes for vertical transient voltage suppressor (TVS) and EMI filter
DE102005009000B4 (de) * 2005-02-28 2009-04-02 Infineon Technologies Austria Ag Vertikales Halbleiterbauelement vom Grabenstrukturtyp und Herstellungsverfahren
US9685524B2 (en) 2005-03-11 2017-06-20 Vishay-Siliconix Narrow semiconductor trench structure
DE102005014744B4 (de) 2005-03-31 2009-06-18 Infineon Technologies Ag Trenchtransistor mit erhöhter Avalanchefestigkeit und Herstellungsverfahren
JP4910304B2 (ja) * 2005-04-20 2012-04-04 トヨタ自動車株式会社 半導体装置
US7648877B2 (en) * 2005-06-24 2010-01-19 Fairchild Semiconductor Corporation Structure and method for forming laterally extending dielectric layer in a trench-gate FET
US7385248B2 (en) 2005-08-09 2008-06-10 Fairchild Semiconductor Corporation Shielded gate field effect transistor with improved inter-poly dielectric
JP4817827B2 (ja) * 2005-12-09 2011-11-16 株式会社東芝 半導体装置
US20070134853A1 (en) * 2005-12-09 2007-06-14 Lite-On Semiconductor Corp. Power semiconductor device having reduced on-resistance and method of manufacturing the same
JP2007189192A (ja) 2005-12-15 2007-07-26 Toshiba Corp 半導体装置
TWI489557B (zh) * 2005-12-22 2015-06-21 維雪 希里康尼克斯公司 高移動率ｐ-通道溝槽及平面型空乏模式的功率型金屬氧化物半導體場效電晶體
US8409954B2 (en) * 2006-03-21 2013-04-02 Vishay-Silconix Ultra-low drain-source resistance power MOSFET
WO2007129261A2 (fr) * 2006-05-05 2007-11-15 Nxp B.V. Transistor à effet de champ en tranchée
DE102006025218B4 (de) 2006-05-29 2009-02-19 Infineon Technologies Austria Ag Leistungshalbleiterbauelement mit Ladungskompensationsstruktur und Verfahren zur Herstellung desselben
DE102006026943B4 (de) * 2006-06-09 2011-01-05 Infineon Technologies Austria Ag Mittels Feldeffekt steuerbarer Trench-Transistor mit zwei Steuerelektroden
JP4241856B2 (ja) * 2006-06-29 2009-03-18 三洋電機株式会社 半導体装置および半導体装置の製造方法
US8154073B2 (en) * 2006-07-14 2012-04-10 Denso Corporation Semiconductor device
KR100741919B1 (ko) 2006-09-12 2007-07-24 동부일렉트로닉스 주식회사 Ｐｎ 접합 게이트 전극을 포함하는 트렌치형 모스트랜지스터 및 그 제조 방법
KR100832718B1 (ko) * 2006-12-27 2008-05-28 동부일렉트로닉스 주식회사 트랜치 게이트 모스 소자 및 그 제조 방법
US9437729B2 (en) 2007-01-08 2016-09-06 Vishay-Siliconix High-density power MOSFET with planarized metalization
US7670908B2 (en) * 2007-01-22 2010-03-02 Alpha & Omega Semiconductor, Ltd. Configuration of high-voltage semiconductor power device to achieve three dimensional charge coupling
DE102007004320A1 (de) * 2007-01-29 2008-07-31 Infineon Technologies Ag Halbleiterbauelement mit vertikalen Strukturen von hohem Aspektverhältnis und Verfahren zur Herstellung einer kapazitiven Struktur in einem Halbleiterkörper
US7595523B2 (en) 2007-02-16 2009-09-29 Power Integrations, Inc. Gate pullback at ends of high-voltage vertical transistor structure
JP5089191B2 (ja) * 2007-02-16 2012-12-05 三菱電機株式会社 半導体装置およびその製造方法
DE102007014038B4 (de) 2007-03-23 2015-02-12 Infineon Technologies Austria Ag Verfahren zur Herstellung eines Halbleiterbauelements
US7615847B2 (en) 2007-03-23 2009-11-10 Infineon Technologies Austria Ag Method for producing a semiconductor component
US9947770B2 (en) 2007-04-03 2018-04-17 Vishay-Siliconix Self-aligned trench MOSFET and method of manufacture
US8368126B2 (en) 2007-04-19 2013-02-05 Vishay-Siliconix Trench metal oxide semiconductor with recessed trench material and remote contacts
JP5183959B2 (ja) * 2007-04-23 2013-04-17 新日本無線株式会社 Ｍｏｓｆｅｔ型半導体装置の製造方法
US8816419B2 (en) * 2007-06-19 2014-08-26 Rohm Co., Ltd. Semiconductor device
DE102007037858B4 (de) 2007-08-10 2012-04-19 Infineon Technologies Ag Halbleiterbauelement mit verbessertem dynamischen Verhalten
US9484451B2 (en) * 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
WO2009055156A1 (fr) * 2007-10-26 2009-04-30 Hvvi Semiconductors, Inc. Structure semi-conductrice et procédé de fabrication
JP5165995B2 (ja) * 2007-11-07 2013-03-21 株式会社東芝 半導体装置及びその製造方法
US7956412B2 (en) * 2007-12-04 2011-06-07 International Business Machines Corporation Lateral diffusion field effect transistor with a trench field plate
EP2091083A3 (fr) * 2008-02-13 2009-10-14 Denso Corporation Dispositif semi-conducteur de carbure de silicium comprenant une couche profonde
WO2009130648A1 (fr) * 2008-04-21 2009-10-29 Nxp B.V. Dispositifs à semi-conducteur comprenant une structure de réduction de champ et leurs procédés de fabrication
JP4918063B2 (ja) * 2008-05-12 2012-04-18 株式会社日立製作所 半導体装置
US7952166B2 (en) * 2008-05-22 2011-05-31 Infineon Technologies Austria Ag Semiconductor device with switch electrode and gate electrode and method for switching a semiconductor device
WO2010001338A1 (fr) * 2008-07-01 2010-01-07 Nxp B.V. Fabrication de dispositifs à semi-conducteur
US8796764B2 (en) * 2008-09-30 2014-08-05 Infineon Technologies Austria Ag Semiconductor device comprising trench gate and buried source electrodes
JP5195357B2 (ja) * 2008-12-01 2013-05-08 トヨタ自動車株式会社 半導体装置
WO2010109596A1 (fr) * 2009-03-24 2010-09-30 トヨタ自動車株式会社 Dispositif à semi-conducteurs
US9425306B2 (en) 2009-08-27 2016-08-23 Vishay-Siliconix Super junction trench power MOSFET devices
US9443974B2 (en) * 2009-08-27 2016-09-13 Vishay-Siliconix Super junction trench power MOSFET device fabrication
US9431530B2 (en) 2009-10-20 2016-08-30 Vishay-Siliconix Super-high density trench MOSFET
JP2011096829A (ja) * 2009-10-29 2011-05-12 Elpida Memory Inc 半導体装置の製造方法
US8198678B2 (en) 2009-12-09 2012-06-12 Infineon Technologies Austria Ag Semiconductor device with improved on-resistance
JP2011159763A (ja) * 2010-01-29 2011-08-18 Toshiba Corp 電力用半導体装置
JP5569162B2 (ja) 2010-06-10 2014-08-13 富士電機株式会社 半導体装置および半導体装置の製造方法
JP5580150B2 (ja) * 2010-09-09 2014-08-27 株式会社東芝 半導体装置
US8362550B2 (en) * 2011-01-20 2013-01-29 Fairchild Semiconductor Corporation Trench power MOSFET with reduced on-resistance
US8461646B2 (en) * 2011-02-04 2013-06-11 Vishay General Semiconductor Llc Trench MOS barrier schottky (TMBS) having multiple floating gates
JP2012204636A (ja) * 2011-03-25 2012-10-22 Toshiba Corp 半導体装置およびその製造方法
JP5450493B2 (ja) * 2011-03-25 2014-03-26 株式会社東芝 半導体装置
WO2012158977A2 (fr) 2011-05-18 2012-11-22 Vishay-Siliconix Dispositif semi-conducteur
JP2013062344A (ja) * 2011-09-13 2013-04-04 Toshiba Corp 半導体装置およびその製造方法
JP5530992B2 (ja) * 2011-09-16 2014-06-25 株式会社東芝 電力用半導体装置
JP2013065774A (ja) 2011-09-20 2013-04-11 Toshiba Corp 半導体装置およびその製造方法
CN103022155B (zh) * 2011-09-26 2017-05-17 盛况 一种沟槽mos结构肖特基二极管及其制备方法
JP5684085B2 (ja) * 2011-10-07 2015-03-11 ルネサスエレクトロニクス株式会社 半導体装置
US9412883B2 (en) 2011-11-22 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for MOS capacitors in replacement gate process
US9431249B2 (en) 2011-12-01 2016-08-30 Vishay-Siliconix Edge termination for super junction MOSFET devices
US9614043B2 (en) * 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
CN103325682A (zh) * 2012-03-20 2013-09-25 上海华虹Nec电子有限公司 双层多晶栅沟槽型mos晶体管的制备方法
TWM435716U (en) * 2012-04-13 2012-08-11 Taiwan Semiconductor Co Ltd The active region of the trench distributed arrangement of the semiconductor device structure
US9685608B2 (en) * 2012-04-13 2017-06-20 Crossbar, Inc. Reduced diffusion in metal electrode for two-terminal memory
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US8669611B2 (en) * 2012-07-11 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for power MOS transistor
US9099419B2 (en) 2012-10-09 2015-08-04 Infineon Technologies Ag Test method and test arrangement
US9455205B2 (en) * 2012-10-09 2016-09-27 Infineon Technologies Ag Semiconductor devices and processing methods
TWI521693B (zh) * 2012-11-27 2016-02-11 財團法人工業技術研究院 蕭基能障二極體及其製造方法
US9799762B2 (en) 2012-12-03 2017-10-24 Infineon Technologies Ag Semiconductor device and method of manufacturing a semiconductor device
DE102013204701A1 (de) * 2013-03-18 2014-10-02 Robert Bosch Gmbh Pseudo-Schottky-Diode
CN103489785A (zh) * 2013-09-03 2014-01-01 上海恺创电子有限公司 超级结半导体器件的元胞结构和工艺实现方法
US9166027B2 (en) 2013-09-30 2015-10-20 Infineon Technologies Ag IGBT with reduced feedback capacitance
US9287404B2 (en) 2013-10-02 2016-03-15 Infineon Technologies Austria Ag Semiconductor device and method of manufacturing a semiconductor device with lateral FET cells and field plates
US9306058B2 (en) 2013-10-02 2016-04-05 Infineon Technologies Ag Integrated circuit and method of manufacturing an integrated circuit
US9224854B2 (en) 2013-10-03 2015-12-29 Texas Instruments Incorporated Trench gate trench field plate vertical MOSFET
US9401399B2 (en) * 2013-10-15 2016-07-26 Infineon Technologies Ag Semiconductor device
US9543396B2 (en) * 2013-12-13 2017-01-10 Power Integrations, Inc. Vertical transistor device structure with cylindrically-shaped regions
JP6199755B2 (ja) * 2014-01-27 2017-09-20 トヨタ自動車株式会社 半導体装置
WO2015114803A1 (fr) * 2014-01-31 2015-08-06 ルネサスエレクトロニクス株式会社 Dispositif semiconducteur
JP6300638B2 (ja) * 2014-05-26 2018-03-28 ルネサスエレクトロニクス株式会社 半導体装置
US9508596B2 (en) 2014-06-20 2016-11-29 Vishay-Siliconix Processes used in fabricating a metal-insulator-semiconductor field effect transistor
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
KR102098996B1 (ko) 2014-08-19 2020-04-08 비쉐이-실리코닉스 초접합 금속 산화물 반도체 전계 효과 트랜지스터
EP3183753B1 (fr) 2014-08-19 2025-03-19 Vishay-Siliconix Dispositif semiconducteur mosfet
JP6274154B2 (ja) * 2015-05-27 2018-02-07 トヨタ自動車株式会社 逆導通ｉｇｂｔ
CN106409677B (zh) * 2015-07-30 2020-03-10 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
JP6416056B2 (ja) 2015-08-26 2018-10-31 株式会社東芝 半導体装置
KR102066310B1 (ko) * 2015-09-08 2020-01-15 매그나칩 반도체 유한회사 전력용 반도체 소자
EP3142149A1 (fr) * 2015-09-11 2017-03-15 Nexperia B.V. Dispositif à semi-conducteurs et procédé de fabrication d'un dispositif à semi-conducteurs
JP6624370B2 (ja) * 2015-09-30 2019-12-25 サンケン電気株式会社 半導体装置
TWI599041B (zh) * 2015-11-23 2017-09-11 節能元件控股有限公司 具有底部閘極之金氧半場效電晶體功率元件及其製作方法
JP6317727B2 (ja) * 2015-12-28 2018-04-25 株式会社東芝 半導体装置
CN107527800B (zh) * 2016-06-22 2021-05-11 无锡华润上华科技有限公司 沟槽栅极结构及其制造方法
CN105914231B (zh) * 2016-06-28 2019-02-05 上海华虹宏力半导体制造有限公司 电荷存储型igbt及其制造方法
CN106328690A (zh) * 2016-09-05 2017-01-11 厦门集顺半导体制造有限公司 具有深槽和t‑poly结构的沟槽型mos肖特基整流器及制造方法
WO2018074427A1 (fr) * 2016-10-17 2018-04-26 富士電機株式会社 Dispositif à semi-conducteur
JP2018152460A (ja) * 2017-03-13 2018-09-27 サンケン電気株式会社 制御装置、及び制御装置とその制御装置により制御される半導体装置とを含むシステム
JP2018157199A (ja) * 2017-03-16 2018-10-04 豊田合成株式会社 ショットキーバリアダイオード
JP2019012813A (ja) * 2017-06-29 2019-01-24 株式会社東芝 絶縁ゲート型バイポーラトランジスタ
JP6761389B2 (ja) * 2017-09-19 2020-09-23 株式会社東芝 半導体装置
JP2018082202A (ja) * 2017-12-27 2018-05-24 ルネサスエレクトロニクス株式会社 半導体装置
JP6873937B2 (ja) * 2018-02-20 2021-05-19 株式会社東芝 半導体装置
JP6992781B2 (ja) * 2018-04-02 2022-01-13 株式会社豊田中央研究所 半導体装置
CN109148587A (zh) * 2018-08-23 2019-01-04 电子科技大学 具有低比导通电阻的分离栅vdmos器件及其制造方法
JP7250473B2 (ja) * 2018-10-18 2023-04-03 三菱電機株式会社 半導体装置
DE102019207761A1 (de) * 2019-05-27 2020-12-03 Robert Bosch Gmbh Verfahren zur Herstellung eines Leistungstransistors und Leistungstransistor
JP7111061B2 (ja) * 2019-05-27 2022-08-02 株式会社デンソー スイッチング素子
JP7242485B2 (ja) * 2019-09-13 2023-03-20 株式会社東芝 半導体装置
US11322612B2 (en) * 2019-09-17 2022-05-03 Kabushiki Kaisha Toshiba Semiconductor device with region of varying thickness
EP3817067A1 (fr) * 2019-10-30 2021-05-05 Nexperia B.V. Dispositif semi-conducteur à transistor mcd et mos combiné
US11158735B2 (en) * 2020-02-05 2021-10-26 Infineon Technologies Austria Ag Charge compensation MOSFET with graded epi profile and methods of manufacturing thereof
KR102315054B1 (ko) 2020-05-15 2021-10-21 현대모비스 주식회사 전력 반도체 소자 및 전력 반도체 칩
KR102369053B1 (ko) * 2020-06-12 2022-03-02 현대모비스 주식회사 전력 반도체 소자 및 그 제조 방법
KR102399430B1 (ko) * 2020-11-02 2022-05-19 현대모비스 주식회사 전력 반도체 소자 및 그 제조 방법
KR102334328B1 (ko) * 2020-05-28 2021-12-02 현대모비스 주식회사 전력 반도체 소자 및 그 제조 방법
KR102309431B1 (ko) * 2020-06-05 2021-10-05 현대모비스 주식회사 전력 반도체 소자 및 그 제조 방법
US11961903B2 (en) 2020-05-26 2024-04-16 Hyundai Mobis Co., Ltd. Power semiconductor device and method of fabricating the same
KR102314770B1 (ko) * 2020-06-02 2021-10-20 현대모비스 주식회사 전력 반도체 소자 및 그 제조 방법
KR102308153B1 (ko) * 2020-06-09 2021-10-05 현대모비스 주식회사 전력 반도체 소자 및 그 제조 방법
KR102314771B1 (ko) * 2020-06-11 2021-10-20 현대모비스 주식회사 전력 반도체 소자 및 그 제조 방법
KR102334327B1 (ko) * 2020-05-28 2021-12-02 현대모비스 주식회사 전력 반도체 소자 및 그 제조 방법
JP7470071B2 (ja) * 2020-07-22 2024-04-17 株式会社東芝 半導体装置
JP7417499B2 (ja) * 2020-09-14 2024-01-18 株式会社東芝 半導体装置の製造方法及び半導体装置
JP7532172B2 (ja) * 2020-09-18 2024-08-13 株式会社東芝 半導体装置
KR102387574B1 (ko) * 2020-09-22 2022-04-19 현대모비스 주식회사 전력 반도체 소자
KR102387575B1 (ko) * 2020-09-22 2022-04-19 현대모비스 주식회사 전력 반도체 소자
TW202215662A (zh) 2020-10-05 2022-04-16 美商電源整合公司 垂直場效電晶體、場效電晶體以及疊接裝置
KR102399429B1 (ko) * 2020-11-02 2022-05-19 현대모비스 주식회사 전력 반도체 소자 및 그 제조 방법
US12389620B2 (en) * 2020-12-30 2025-08-12 Stmicroelectronics S.R.L. Split-gate trench MOS transistor with self-alignment of gate and body regions
US20220271131A1 (en) * 2021-02-23 2022-08-25 Changxin Memory Technologies, Inc. Semiconductor structure and method for forming same
CN113013229A (zh) * 2021-02-25 2021-06-22 厦门大学 一种碳化硅umosfet功率器件及其制备方法
CN113410309A (zh) * 2021-06-23 2021-09-17 电子科技大学 一种低比导通电阻的分立栅mosfet器件及其制造方法
CN113394298B (zh) * 2021-06-23 2023-06-16 电子科技大学 一种超低比导通电阻的ldmos器件及其制造方法
JP7739064B2 (ja) * 2021-06-25 2025-09-16 三菱電機株式会社 絶縁ゲートバイポーラトランジスタおよびゲートドライバ回路
US20230010328A1 (en) * 2021-07-06 2023-01-12 Nami MOS CO., LTD. Shielded gate trench mosfet with multiple stepped epitaxial structures
KR102572223B1 (ko) * 2021-07-08 2023-08-30 현대모비스 주식회사 전력 반도체 소자 및 그 제조 방법
JP7614986B2 (ja) * 2021-09-10 2025-01-16 株式会社東芝 半導体装置
EP4173048A1 (fr) * 2021-09-15 2023-05-03 Dynex Semiconductor Limited Dispositif igbt avec bus de grille en tranchée
CN114335140B (zh) * 2021-12-16 2026-03-27 无锡先瞳半导体科技有限公司 三维隔离型超结结构场效应晶体管及其制备方法
US12176397B2 (en) * 2022-01-03 2024-12-24 Nami MOS CO., LTD. Super barrier rectifier with shielded gate electrode and multiple stepped epitaxial structure
CN114744037B (zh) * 2022-02-28 2026-01-27 无锡先瞳半导体科技有限公司 变掺杂浓度结构的屏蔽栅沟槽型场效应晶体管及制备方法
US12266726B2 (en) * 2022-04-07 2025-04-01 Nami MOS CO., LTD. Shielded gate trench MOSFETs with improved performance structures
US20230411302A1 (en) * 2022-06-15 2023-12-21 Texas Instruments Incorporated Deep trench bypass capacitor for electromagnetic interference noise reduction
JP7748346B2 (ja) * 2022-09-16 2025-10-02 株式会社東芝 半導体装置

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4754310A (en) 1980-12-10 1988-06-28 U.S. Philips Corp. High voltage semiconductor device
US4941026A (en) 1986-12-05 1990-07-10 General Electric Company Semiconductor devices exhibiting minimum on-resistance
JPH03109775A (ja) * 1989-09-25 1991-05-09 Hitachi Ltd 絶縁ゲート型半導体装置
WO1994003922A1 (fr) 1992-08-07 1994-02-17 Advanced Power Technology, Inc. Structure de dispositif de puissance a haute densite et procede pour sa fabrication
US5637898A (en) 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
DE19604043A1 (de) 1996-02-05 1997-08-07 Siemens Ag Durch Feldeffekt steuerbares Halbleiterbauelement
WO1997035346A1 (fr) 1996-03-20 1997-09-25 Siemens Aktiengesellschaft Composant a semi-conducteur commande par effet de champ
US5998833A (en) * 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
US5998883A (en) 1998-03-19 1999-12-07 Jidosha Denki Kogyo Kabushiki Kaisha Wiper control device
DE19848828A1 (de) 1998-10-22 2000-05-04 Siemens Ag Halbleiterbauelement mit kleiner Durchlaßspannung und hoher Sperrfähigkeit
WO2000033385A1 (fr) 1998-11-27 2000-06-08 Infineon Technologies Ag Transistor mos a effet de champ avec electrode auxiliaire
JP3109775B2 (ja) 1993-02-18 2000-11-20 永大産業株式会社 木質材の熱処理方法
JP2000349288A (ja) 1999-06-09 2000-12-15 Fuji Electric Co Ltd 縦型ｍｏｓｆｅｔ
DE10007415A1 (de) 2000-02-18 2001-09-06 Infineon Technologies Ag Halbleiterbauelement

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2570742B2 (ja) * 1987-05-27 1997-01-16 ソニー株式会社 半導体装置
JP2941823B2 (ja) * 1988-11-28 1999-08-30 株式会社日立製作所 半導体装置及びその製造方法
US5126807A (en) * 1990-06-13 1992-06-30 Kabushiki Kaisha Toshiba Vertical MOS transistor and its production method
JP2753155B2 (ja) * 1990-06-13 1998-05-18 株式会社東芝 縦型ｍｏｓトランジスタとその製造方法
NL9102009A (nl) * 1991-11-29 1993-06-16 Stichting Katholieke Univ Produktie van bioactieve peptiden met recombinante cellen.
JP2837014B2 (ja) * 1992-02-17 1998-12-14 三菱電機株式会社 半導体装置及びその製造方法
JP3383377B2 (ja) * 1993-10-28 2003-03-04 株式会社東芝 トレンチ構造の縦型のノーマリーオン型のパワーｍｏｓｆｅｔおよびその製造方法
JP3307785B2 (ja) * 1994-12-13 2002-07-24 三菱電機株式会社 絶縁ゲート型半導体装置
JP3405649B2 (ja) * 1996-12-05 2003-05-12 株式会社東芝 半導体装置
JP3744175B2 (ja) * 1997-02-14 2006-02-08 株式会社デンソー 炭化珪素半導体装置及びその製造方法
JPH1140808A (ja) * 1997-05-21 1999-02-12 Toyota Motor Corp 半導体装置およびその製造方法
US6337499B1 (en) * 1997-11-03 2002-01-08 Infineon Technologies Ag Semiconductor component
EP1026749B1 (fr) * 1998-07-23 2003-09-17 Mitsubishi Denki Kabushiki Kaisha Méthode de fabrication d'un dispositif semi-conducteur et dispositif semi-conducteur ainsi obtenable
JP2000156978A (ja) * 1998-11-17 2000-06-06 Fuji Electric Co Ltd ソフトスイッチング回路
JP3971062B2 (ja) * 1999-07-29 2007-09-05 株式会社東芝 高耐圧半導体装置
DE19958694A1 (de) * 1999-12-06 2001-06-13 Infineon Technologies Ag Steuerbares Halbleiterschaltelement
EP1162665A3 (fr) * 2000-06-08 2002-10-09 Siliconix Incorporated Dispositif MIS à grille en tranchée et sa méthode de fabrication
JP4528460B2 (ja) * 2000-06-30 2010-08-18 株式会社東芝 半導体素子
US6586833B2 (en) * 2000-11-16 2003-07-01 Silicon Semiconductor Corporation Packaged power devices having vertical power mosfets therein that are flip-chip mounted to slotted gate electrode strip lines
US6677641B2 (en) * 2001-10-17 2004-01-13 Fairchild Semiconductor Corporation Semiconductor structure with improved smaller forward voltage loss and higher blocking capability
US6784488B2 (en) * 2001-11-16 2004-08-31 Koninklijke Philips Electronics N.V. Trench-gate semiconductor devices and the manufacture thereof
JP2004022941A (ja) 2002-06-19 2004-01-22 Toshiba Corp 半導体装置
US6906380B1 (en) * 2004-05-13 2005-06-14 Vishay-Siliconix Drain side gate trench metal-oxide-semiconductor field effect transistor

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4754310A (en) 1980-12-10 1988-06-28 U.S. Philips Corp. High voltage semiconductor device
US4941026A (en) 1986-12-05 1990-07-10 General Electric Company Semiconductor devices exhibiting minimum on-resistance
US5801417A (en) * 1988-05-17 1998-09-01 Advanced Power Technology, Inc. Self-aligned power MOSFET device with recessed gate and source
JPH03109775A (ja) * 1989-09-25 1991-05-09 Hitachi Ltd 絶縁ゲート型半導体装置
WO1994003922A1 (fr) 1992-08-07 1994-02-17 Advanced Power Technology, Inc. Structure de dispositif de puissance a haute densite et procede pour sa fabrication
JP3109775B2 (ja) 1993-02-18 2000-11-20 永大産業株式会社 木質材の熱処理方法
US5637898A (en) 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
DE19604043A1 (de) 1996-02-05 1997-08-07 Siemens Ag Durch Feldeffekt steuerbares Halbleiterbauelement
WO1997035346A1 (fr) 1996-03-20 1997-09-25 Siemens Aktiengesellschaft Composant a semi-conducteur commande par effet de champ
US5998883A (en) 1998-03-19 1999-12-07 Jidosha Denki Kogyo Kabushiki Kaisha Wiper control device
DE19848828A1 (de) 1998-10-22 2000-05-04 Siemens Ag Halbleiterbauelement mit kleiner Durchlaßspannung und hoher Sperrfähigkeit
US5998833A (en) * 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
WO2000033385A1 (fr) 1998-11-27 2000-06-08 Infineon Technologies Ag Transistor mos a effet de champ avec electrode auxiliaire
JP2000349288A (ja) 1999-06-09 2000-12-15 Fuji Electric Co Ltd 縦型ｍｏｓｆｅｔ
DE10007415A1 (de) 2000-02-18 2001-09-06 Infineon Technologies Ag Halbleiterbauelement

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Merchant, S., "Dependence of Breakdown Voltage on Drift Length and Buried Oxide Thickness of SOI RESURF LDMOS Transistors," Institute of Electrical and Electronics Engineers, 1993, pp. 124-128.

Cited By (190)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7531871B2 (en) * 2000-06-30 2009-05-12 Kabushiki Kaisha Toshiba Power semiconductor switching element
US7067870B2 (en) * 2000-06-30 2006-06-27 Kabushiki Kaisha Toshiba Power semiconductor switching element
US20060145230A1 (en) * 2000-06-30 2006-07-06 Ichiro Omura Power semiconductor switching element
US20040155287A1 (en) * 2000-06-30 2004-08-12 Ichiro Omura Power semiconductor switching element
US9368587B2 (en) 2001-01-30 2016-06-14 Fairchild Semiconductor Corporation Accumulation-mode field effect transistor with improved current capability
US8829641B2 (en) 2001-01-30 2014-09-09 Fairchild Semiconductor Corporation Method of forming a dual-trench field effect transistor
US7345342B2 (en) 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US20110018058A1 (en) * 2001-09-07 2011-01-27 Power Integrations, Inc. High-voltage vertical transistor with edge termination structure
US8552496B2 (en) * 2001-09-07 2013-10-08 Power Integrations, Inc. High-voltage vertical transistor with edge termination structure
US7786533B2 (en) * 2001-09-07 2010-08-31 Power Integrations, Inc. High-voltage vertical transistor with edge termination structure
US20050167749A1 (en) * 2001-09-07 2005-08-04 Power Integrations, Inc. High-voltage vertical transistor with edge termination structure
US7429523B2 (en) 2001-10-17 2008-09-30 Fairchild Semiconductor Corporation Method of forming schottky diode with charge balance structure
USRE46799E1 (en) * 2002-09-25 2018-04-17 Kabushiki Kaisha Toshiba Semiconductor device with alternating conductivity type layers having different vertical impurity concentration profiles
US7582519B2 (en) 2002-11-05 2009-09-01 Fairchild Semiconductor Corporation Method of forming a trench structure having one or more diodes embedded therein adjacent a PN junction
US7075149B2 (en) 2003-05-13 2006-07-11 Kabushiki Kaisha Toshiba Semiconductor device and its manufacturing method
US20050006699A1 (en) * 2003-05-13 2005-01-13 Kabushiki Kaisha Toshiba Semiconductor device and its manufacturing method
US20090008706A1 (en) * 2003-05-20 2009-01-08 Yedinak Joseph A Power Semiconductor Devices with Shield and Gate Contacts and Methods of Manufacture
US8889511B2 (en) * 2003-05-20 2014-11-18 Fairchild Semiconductor Corporation Methods of manufacturing power semiconductor devices with trenched shielded split gate transistor
US8936985B2 (en) * 2003-05-20 2015-01-20 Fairchild Semiconductor Corporation Methods related to power semiconductor devices with thick bottom oxide layers
US8786045B2 (en) 2003-05-20 2014-07-22 Fairchild Semiconductor Corporation Power semiconductor devices having termination structures
US8013391B2 (en) * 2003-05-20 2011-09-06 Fairchild Semiconductor Corporation Power semiconductor devices with trenched shielded split gate transistor and methods of manufacture
US20120220091A1 (en) * 2003-05-20 2012-08-30 Ashok Challa Methods of making power semiconductor devices with thick bottom oxide layer
US7982265B2 (en) * 2003-05-20 2011-07-19 Fairchild Semiconductor Corporation Trenched shield gate power semiconductor devices and methods of manufacture
US7638841B2 (en) * 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US8129245B2 (en) * 2003-05-20 2012-03-06 Fairchild Semiconductor Corporation Methods of manufacturing power semiconductor devices with shield and gate contacts
US8350317B2 (en) 2003-05-20 2013-01-08 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US8013387B2 (en) * 2003-05-20 2011-09-06 Fairchild Semiconductor Corporation Power semiconductor devices with shield and gate contacts and methods of manufacture
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US8143123B2 (en) 2003-05-20 2012-03-27 Fairchild Semiconductor Corporation Methods of forming inter-poly dielectric (IPD) layers in power semiconductor devices
US7855415B2 (en) 2003-05-20 2010-12-21 Fairchild Semiconductor Corporation Power semiconductor devices having termination structures and methods of manufacture
US8143124B2 (en) 2003-05-20 2012-03-27 Fairchild Semiconductor Corporation Methods of making power semiconductor devices with thick bottom oxide layer
US7622742B2 (en) * 2003-07-03 2009-11-24 Epivalley Co., Ltd. III-nitride compound semiconductor light emitting device
US20070114511A1 (en) * 2003-07-03 2007-05-24 Epivalley Co., Ltd. lll-Nitride compound semiconductor light emiting device
US20070108515A1 (en) * 2003-11-29 2007-05-17 Koninklijke Philips Electronics, N.V. Trench mosfet
US20050253190A1 (en) * 2004-04-09 2005-11-17 Kabushiki Kaisha Toshiba Semiconductor device
US8148233B2 (en) 2004-08-03 2012-04-03 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
US8026558B2 (en) 2004-08-03 2011-09-27 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
US7352036B2 (en) 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
US7732876B2 (en) 2004-08-03 2010-06-08 Fairchild Semiconductor Corporation Power transistor with trench sinker for contacting the backside
US20060214197A1 (en) * 2005-02-22 2006-09-28 Kabushiki Kaisha Toshiba Semiconductor device
WO2006108011A3 (fr) * 2005-04-06 2007-04-05 Fairchild Semiconductor Transistors a effet de champ a grille en tranchees, et procedes de creation desdits transistors
US8084327B2 (en) * 2005-04-06 2011-12-27 Fairchild Semiconductor Corporation Method for forming trench gate field effect transistor with recessed mesas using spacers
CN102867825B (zh) * 2005-04-06 2016-04-06 飞兆半导体公司 沟栅场效应晶体管结构及其形成方法
US7504306B2 (en) 2005-04-06 2009-03-17 Fairchild Semiconductor Corporation Method of forming trench gate field effect transistor with recessed mesas
US8680611B2 (en) 2005-04-06 2014-03-25 Fairchild Semiconductor Corporation Field effect transistor and schottky diode structures
CN102867825A (zh) * 2005-04-06 2013-01-09 飞兆半导体公司 沟栅场效应晶体管结构及其形成方法
CN101185169B (zh) * 2005-04-06 2010-08-18 飞兆半导体公司 沟栅场效应晶体管及其形成方法
US8232610B2 (en) 2005-05-20 2012-07-31 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
US8592920B2 (en) 2005-05-20 2013-11-26 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
US9013006B2 (en) 2005-05-20 2015-04-21 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
US8604563B2 (en) 2005-05-20 2013-12-10 Renesas Electronics Corporation Semiconductor device and manufacturing method of the same
US20100327359A1 (en) * 2005-05-20 2010-12-30 Yoshito Nakazawa Semiconductor device and manufacturing method of the same
US8043913B2 (en) 2005-05-26 2011-10-25 Fairchild Semiconductor Corporation Method of forming trench-gate field effect transistors
US20110177662A1 (en) * 2005-05-26 2011-07-21 Hamza Yilmaz Method of Forming Trench-Gate Field Effect Transistors
US20060273386A1 (en) * 2005-05-26 2006-12-07 Hamza Yilmaz Trench-gate field effect transistors and methods of forming the same
US20090230465A1 (en) * 2005-05-26 2009-09-17 Hamza Yilmaz Trench-Gate Field Effect Transistors and Methods of Forming the Same
US7504303B2 (en) 2005-05-26 2009-03-17 Fairchild Semiconductor Corporation Trench-gate field effect transistors and methods of forming the same
US20100258862A1 (en) * 2005-05-26 2010-10-14 Fairchild Semiconductor Corporation Trench-gate field effect transistor with channel enhancement region and methods of forming the same
US7923776B2 (en) 2005-05-26 2011-04-12 Fairchild Semiconductor Corporation Trench-gate field effect transistor with channel enhancement region and methods of forming the same
US8884365B2 (en) 2005-05-26 2014-11-11 Fairchild Semiconductor Corporation Trench-gate field effect transistor
US8441069B2 (en) 2005-05-26 2013-05-14 Fairchild Semiconductor Corporation Structure and method for forming trench-gate field effect transistor with source plug
US7767524B2 (en) 2005-06-10 2010-08-03 Fairchild Semiconductor Corporatiion Method and structure for forming a shielded gate field effect transistor
US20100258855A1 (en) * 2005-06-10 2010-10-14 Hamza Yilmaz Field Effect Transistor with Self-aligned Source and Heavy Body Regions and Method of Manufacturing Same
US20090191678A1 (en) * 2005-06-10 2009-07-30 Hamza Yilmaz Method of Forming a Shielded Gate Field Effect Transistor
US7514322B2 (en) 2005-06-10 2009-04-07 Fairchild Semiconductor Corporation Shielded gate field effect transistor
US20100038708A1 (en) * 2005-06-10 2010-02-18 Hamza Yilmaz Method and Structure for Forming a Shielded Gate Field Effect Transistor
US7955920B2 (en) 2005-06-10 2011-06-07 Fairchild Semiconductor Corporation Field effect transistor with self-aligned source and heavy body regions and method of manufacturing same
US7625799B2 (en) 2005-06-10 2009-12-01 Fairchild Semiconductor Corporation Method of forming a shielded gate field effect transistor
US8278705B2 (en) 2005-06-10 2012-10-02 Fairchild Semiconductor Corporation Field effect transistor with gated and non-gated trenches
US8592895B2 (en) 2005-06-10 2013-11-26 Fairchild Semiconductor Corporation Field effect transistor with source, heavy body region and shielded gate
US7935577B2 (en) * 2005-06-29 2011-05-03 Fairchild Semiconductor Corporation Method for forming shielded gate field effect transistor using spacers
US8803207B2 (en) 2005-06-29 2014-08-12 Fairchild Semiconductor Corporation Shielded gate field effect transistors
US20110212586A1 (en) * 2005-06-29 2011-09-01 Grebs Thomas E Method for Forming Shielded Gate Field Effect Transistors
US20090111231A1 (en) * 2005-06-29 2009-04-30 Grebs Thomas E Method for Forming Shielded Gate Field Effect Transistor Using Spacers
US7915617B2 (en) 2005-07-04 2011-03-29 Kabushiki Kaisha Toshiba Semiconductor device
US20070007537A1 (en) * 2005-07-04 2007-01-11 Kabushiki Kaisha Toshiba Semiconductor device
US8193570B2 (en) 2006-01-05 2012-06-05 Fairchild Semiconductor Corporation Synchronous buck converter using shielded gate field effect transistors
US20110163732A1 (en) * 2006-01-05 2011-07-07 Steven Sapp Synchronous buck converter using shielded gate field effect transistors
US20080017920A1 (en) * 2006-01-05 2008-01-24 Steven Sapp Structure and method for improving shielded gate field effect transistors
US7768064B2 (en) 2006-01-05 2010-08-03 Fairchild Semiconductor Corporation Structure and method for improving shielded gate field effect transistors
US7446374B2 (en) 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US7473603B2 (en) 2006-06-19 2009-01-06 Fairchild Semiconductor Corporation Method for forming a shielded gate trench FET with the shield and gate electrodes being connected together
US7859047B2 (en) 2006-06-19 2010-12-28 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes connected together in non-active region
US7319256B1 (en) 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
US7642597B2 (en) 2006-11-14 2010-01-05 Kabushiki Kaisha Toshiba Power semiconductor device
US20080135930A1 (en) * 2006-11-14 2008-06-12 Kabushiki Kaisha Toshiba Power semiconductor device
US8698234B2 (en) * 2006-12-01 2014-04-15 Infineon Technologies Austria Ag Electronic device with connecting structure
US20080173876A1 (en) * 2007-01-18 2008-07-24 Fuji Electric Device Technology Co., Ltd. Insulated gate silicon carbide semiconductor device
US7700971B2 (en) * 2007-01-18 2010-04-20 Fuji Electric Device Technology Co., Ltd. Insulated gate silicon carbide semiconductor device
US7791135B2 (en) 2007-01-29 2010-09-07 Fuji Electric Systems Co., Ltd. Insulated gate silicon carbide semiconductor device and method for manufacturing the same
US20100285647A1 (en) * 2007-01-29 2010-11-11 Fuji Electric Systems Co., Ltd. Insulated gate silicon carbide semiconductor device and method for manufacturing the same
US20080197361A1 (en) * 2007-01-29 2008-08-21 Fuji Electric Device Technology Co., Ltd. Insulated gate silicon carbide semiconductor device and method for manufacturing the same
US8039346B2 (en) 2007-01-29 2011-10-18 Fuji Electric Co., Ltd. Insulated gate silicon carbide semiconductor device and method for manufacturing the same
US20090051000A1 (en) * 2007-08-21 2009-02-26 Jeng Gong Semiconductor device structure
US8928077B2 (en) 2007-09-21 2015-01-06 Fairchild Semiconductor Corporation Superjunction structures for power devices
US9595596B2 (en) 2007-09-21 2017-03-14 Fairchild Semiconductor Corporation Superjunction structures for power devices
US20100013008A1 (en) * 2008-03-12 2010-01-21 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US8907407B2 (en) * 2008-03-12 2014-12-09 Semiconductor Components Industries, Llc Semiconductor device covered by front electrode layer and back electrode layer
US20100320534A1 (en) * 2008-06-20 2010-12-23 James Pan Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices
US8669623B2 (en) 2008-06-20 2014-03-11 Fairchild Semiconductor Corporation Structure related to a thick bottom dielectric (TBD) for trench-gate devices
US20100163950A1 (en) * 2008-06-30 2010-07-01 Jon Gladish Power Device with Monolithically Integrated RC Snubber
US8829624B2 (en) 2008-06-30 2014-09-09 Fairchild Semiconductor Corporation Power device with monolithically integrated RC snubber
US20100123188A1 (en) * 2008-11-14 2010-05-20 Prasad Venkatraman Semiconductor device having trench shield electrode structure
TWI470800B (zh) * 2008-11-14 2015-01-21 半導體組件工業公司 用於具有溝槽遮罩電極的半導體裝置的接觸結構和方法
US20100123187A1 (en) * 2008-11-14 2010-05-20 Burke Peter A Contact structure for semiconductor device having trench shield electrode and method
CN101740612A (zh) * 2008-11-14 2010-06-16 半导体元件工业有限责任公司 用于具有槽屏蔽电极的半导体器件的接触结构和方法
US8362548B2 (en) * 2008-11-14 2013-01-29 Semiconductor Components Industries, Llc Contact structure for semiconductor device having trench shield electrode and method
CN101740612B (zh) * 2008-11-14 2014-02-26 半导体元件工业有限责任公司 用于具有槽屏蔽电极的半导体器件的接触结构和方法
US8552535B2 (en) 2008-11-14 2013-10-08 Semiconductor Components Industries, Llc Trench shielding structure for semiconductor device and method
US7915672B2 (en) 2008-11-14 2011-03-29 Semiconductor Components Industries, L.L.C. Semiconductor device having trench shield electrode structure
US9306018B2 (en) 2008-11-14 2016-04-05 Semiconductor Components Industries, Llc Trench shielding structure for semiconductor device and method
US20100140697A1 (en) * 2008-12-08 2010-06-10 Yedinak Joseph A Trench-Based Power Semiconductor Devices with Increased Breakdown Voltage Characteristics
US9293526B2 (en) 2008-12-08 2016-03-22 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8564024B2 (en) 2008-12-08 2013-10-22 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US20100140696A1 (en) * 2008-12-08 2010-06-10 Yedinak Joseph A Trench-Based Power Semiconductor Devices With Increased Breakdown Voltage Characteristics
US9391193B2 (en) 2008-12-08 2016-07-12 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US9748329B2 (en) 2008-12-08 2017-08-29 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US10868113B2 (en) 2008-12-08 2020-12-15 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8563377B2 (en) 2008-12-08 2013-10-22 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US20100140695A1 (en) * 2008-12-08 2010-06-10 Yedinak Joseph A Trench-Based Power Semiconductor Devices With Increased Breakdown Voltage Characteristics
US20100140689A1 (en) * 2008-12-08 2010-06-10 Yedinak Joseph A Trench-Based Power Semiconductor Devices with Increased Breakdown Voltage Characteristics
US8963212B2 (en) 2008-12-08 2015-02-24 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8932924B2 (en) 2008-12-08 2015-01-13 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8304829B2 (en) 2008-12-08 2012-11-06 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8174067B2 (en) 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8193581B2 (en) 2008-12-08 2012-06-05 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8227855B2 (en) 2009-02-09 2012-07-24 Fairchild Semiconductor Corporation Semiconductor devices with stable and controlled avalanche characteristics and methods of fabricating the same
US20100200910A1 (en) * 2009-02-09 2010-08-12 Joseph Yedinak Semiconductor Devices with Stable and Controlled Avalanche Characteristics and Methods of Fabricating the Same
US20100207205A1 (en) * 2009-02-19 2010-08-19 Grebs Thomas E Structures and Methods for Improving Trench-Shielded Semiconductor Devices and Schottky Barrier Rectifier Devices
US8148749B2 (en) 2009-02-19 2012-04-03 Fairchild Semiconductor Corporation Trench-shielded semiconductor device
US20100314707A1 (en) * 2009-06-12 2010-12-16 Yedinak Joseph A Reduced Process Sensitivity of Electrode-Semiconductor Rectifiers
US8049276B2 (en) 2009-06-12 2011-11-01 Fairchild Semiconductor Corporation Reduced process sensitivity of electrode-semiconductor rectifiers
US8492837B2 (en) 2009-06-12 2013-07-23 Fairchild Semiconductor Corporation Reduced process sensitivity of electrode-semiconductor rectifiers
US7952141B2 (en) 2009-07-24 2011-05-31 Fairchild Semiconductor Corporation Shield contacts in a shielded gate MOSFET
US20110018059A1 (en) * 2009-07-24 2011-01-27 Dixie Dunn Shield Contacts in a Shielded Gate MOSFET
US8338285B2 (en) 2009-07-24 2012-12-25 Fairchild Semiconductor Corporation Shield contacts in a shielded gate MOSFET
US20110049615A1 (en) * 2009-08-25 2011-03-03 Kabushiki Kaisha Toshiba Power semiconductor device
US8680608B2 (en) 2009-08-25 2014-03-25 Kabushiki Kaisha Toshiba Power semiconductor device with a low on resistence
US20120292693A1 (en) * 2009-08-31 2012-11-22 Alpha & Omega Semiconductor Incorporated Fabrication of trench dmos device having thick bottom shielding oxide
US9000514B2 (en) * 2009-08-31 2015-04-07 Alpha And Omega Semiconductor Incorporated Fabrication of trench DMOS device having thick bottom shielding oxide
US8319290B2 (en) 2010-06-18 2012-11-27 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
US8432000B2 (en) 2010-06-18 2013-04-30 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
CN102403315B (zh) * 2010-09-07 2014-06-25 株式会社东芝 半导体装置
CN102403315A (zh) * 2010-09-07 2012-04-04 株式会社东芝 半导体装置
US20140332845A1 (en) * 2010-10-31 2014-11-13 Madhur Bobde Topside structures for an insulated gate bipolar transistor (igbt) device to achieve improved device perforemances
US10686062B2 (en) * 2010-10-31 2020-06-16 Alpha And Omega Semiconductor Incorporated Topside structures for an insulated gate bipolar transistor (IGBT) device to achieve improved device performances
US9153677B2 (en) * 2012-04-25 2015-10-06 Abb Schweiz Ag Insulated gate bipolar transistor with high emitter gate capacitance
US20150028382A1 (en) * 2012-04-25 2015-01-29 Abb Schweiz Ag Insulated gate bipolar transistor with high emitter gate capacitance
US8921184B2 (en) 2012-05-14 2014-12-30 Semiconductor Components Industries, Llc Method of making an electrode contact structure and structure therefor
US9029215B2 (en) 2012-05-14 2015-05-12 Semiconductor Components Industries, Llc Method of making an insulated gate semiconductor device having a shield electrode structure
US10355125B2 (en) 2012-05-14 2019-07-16 Semiconductor Components Industries, Llc Electrode contact structure for semiconductor device
CN104380471A (zh) * 2012-06-13 2015-02-25 株式会社电装 碳化硅半导体装置及其制造方法
CN104380471B (zh) * 2012-06-13 2017-10-27 株式会社电装 碳化硅半导体装置及其制造方法
US9502555B2 (en) * 2012-06-15 2016-11-22 Magnachip Semiconductor, Ltd. Semiconductor device and fabricating method thereof
US20130334596A1 (en) * 2012-06-15 2013-12-19 Magnachip Semiconductor, Ltd. Semiconductor device and fabricating method thereof
CN103681851A (zh) * 2012-09-12 2014-03-26 株式会社东芝 电力半导体元件
US9496391B2 (en) 2013-03-15 2016-11-15 Fairchild Semiconductor Corporation Termination region of a semiconductor device
US10749027B2 (en) 2013-03-15 2020-08-18 Fairchild Semiconductor Corporation Methods and apparatus related to termination regions of a semiconductor device
US10249721B2 (en) 2013-04-04 2019-04-02 Infineon Technologies Austria Ag Semiconductor device including a gate trench and a source trench
US10636883B2 (en) 2013-04-04 2020-04-28 Infineon Technologies Austria Ag Semiconductor device including a gate trench and a source trench
US9818743B2 (en) 2013-06-21 2017-11-14 Infineon Technologies Americas Corp. Power semiconductor device with contiguous gate trenches and offset source trenches
US10192960B2 (en) * 2013-07-26 2019-01-29 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing same
US20160181372A1 (en) * 2013-07-26 2016-06-23 Sumitomo Electric Industries, Ltd. Silicon carbide semiconductor device and method for manufacturing same
US10629676B2 (en) 2013-08-09 2020-04-21 Infineon Technologies Ag Semiconductor device with cell trench structures and recessed contacts and method of manufacturing a semiconductor device
US9666663B2 (en) 2013-08-09 2017-05-30 Infineon Technologies Ag Semiconductor device with cell trench structures and contacts and method of manufacturing a semiconductor device
US9653568B2 (en) 2013-09-13 2017-05-16 Infineon Technologies Ag Method of manufacturing an insulated gate bipolar transistor with mesa sections between cell trench structures
US9076838B2 (en) 2013-09-13 2015-07-07 Infineon Technologies Ag Insulated gate bipolar transistor with mesa sections between cell trench structures and method of manufacturing
US9711641B2 (en) 2013-11-27 2017-07-18 Infineon Technologies Ag Semiconductor device with cell trench structures and a contact structure
US9385228B2 (en) 2013-11-27 2016-07-05 Infineon Technologies Ag Semiconductor device with cell trench structures and contacts and method of manufacturing a semiconductor device
US9105679B2 (en) 2013-11-27 2015-08-11 Infineon Technologies Ag Semiconductor device and insulated gate bipolar transistor with barrier regions
US20190393314A1 (en) * 2013-12-13 2019-12-26 Power Integrations, Inc. Vertical Transistor Device Structure with Cylindrical-Shaped Field Plates
US9553179B2 (en) 2014-01-31 2017-01-24 Infineon Technologies Ag Semiconductor device and insulated gate bipolar transistor with barrier structure
DE102014119395A1 (de) * 2014-12-22 2016-06-23 Infineon Technologies Ag Transistorbauelement mit Feldelektrode
DE102014119395B4 (de) 2014-12-22 2022-10-06 Infineon Technologies Ag Transistorbauelement mit Feldelektrode
US9698228B2 (en) 2014-12-22 2017-07-04 Infineon Technologies Ag Transistor device with field-electrode
CN105720102B (zh) * 2014-12-22 2019-01-25 英飞凌科技股份有限公司 具有场电极的晶体管器件
CN105720102A (zh) * 2014-12-22 2016-06-29 英飞凌科技股份有限公司 具有场电极的晶体管器件
US10068975B2 (en) 2015-01-13 2018-09-04 Infineon Technologies Austria Ag Semiconductor device having field plate structures, source regions and gate electrode structures between the field plate structures
US9691862B2 (en) 2015-01-13 2017-06-27 Infineon Technologies Austria Ag Semiconductor device having field plate structures and gate electrode structures between the field plate structures
DE102015100390A1 (de) * 2015-01-13 2016-07-14 Infineon Technologies Austria Ag Halbleitervorrichtung mit feldplattenstrukturen und gateelektrodenstrukturen zwischen den feldplattenstrukturen sowie herstellungsverfahren
DE102015100390B4 (de) * 2015-01-13 2021-02-11 Infineon Technologies Austria Ag Halbleitervorrichtung mit feldplattenstrukturen und gateelektrodenstrukturen zwischen den feldplattenstrukturen sowie herstellungsverfahren
CN105957884A (zh) * 2016-06-24 2016-09-21 上海格瑞宝电子有限公司 一种分栅栅极沟槽结构和沟槽肖特基二极管及其制备方法
US12080792B2 (en) 2019-04-23 2024-09-03 Denso Corporation Semiconductor device and method for manufacturing same
WO2021088156A1 (fr) * 2019-11-08 2021-05-14 株洲中车时代电气股份有限公司 Dispositif à semi-conducteur de puissance
CN112786695B (zh) * 2019-11-08 2022-05-03 株洲中车时代电气股份有限公司 一种分裂栅沟槽功率半导体器件
CN112786695A (zh) * 2019-11-08 2021-05-11 株洲中车时代电气股份有限公司 一种分裂栅沟槽功率半导体器件
US20210249535A1 (en) * 2020-02-07 2021-08-12 Rohm Co., Ltd. Semiconductor device
US12051743B2 (en) * 2020-02-07 2024-07-30 Rohm Co., Ltd. Semiconductor device
US12426341B2 (en) * 2021-03-01 2025-09-23 Wolfspeed, Inc. Semiconductor devices having gate resistors with low variation in resistance values
US12356694B2 (en) 2022-03-23 2025-07-08 Kabushiki Kaisha Toshiba Semiconductor device

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