JPH01116458U - - Google Patents
Info
- Publication number
- JPH01116458U JPH01116458U JP1988012082U JP1208288U JPH01116458U JP H01116458 U JPH01116458 U JP H01116458U JP 1988012082 U JP1988012082 U JP 1988012082U JP 1208288 U JP1208288 U JP 1208288U JP H01116458 U JPH01116458 U JP H01116458U
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead frame
- utility
- scope
- registration request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は、本考案に係るリードフレームの平面
図、第２図は、そのリード線の断面図、第３図は
、従来のリードフレームの平面図、第４図は、樹
脂封止方法を説明するための断面図である。 Ａ…樹脂封止位置、２２…リード線、２４…放
熱板兼アイランド、Ｂ…粗面。
図、第２図は、そのリード線の断面図、第３図は
、従来のリードフレームの平面図、第４図は、樹
脂封止方法を説明するための断面図である。 Ａ…樹脂封止位置、２２…リード線、２４…放
熱板兼アイランド、Ｂ…粗面。
Claims (1)
- 樹脂封止位置に隣接するリード線、放熱板等の
外部露出部表面を粗面にしたことを特徴とするリ
ードフレーム。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988012082U JPH01116458U (ja) | 1988-01-29 | 1988-01-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988012082U JPH01116458U (ja) | 1988-01-29 | 1988-01-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01116458U true JPH01116458U (ja) | 1989-08-07 |
Family
ID=31221208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988012082U Pending JPH01116458U (ja) | 1988-01-29 | 1988-01-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01116458U (ja) |
-
1988
- 1988-01-29 JP JP1988012082U patent/JPH01116458U/ja active Pending